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1. 发明授权

US5173755A Capacitively induced electrostatic discharge protection circuit 失效
标题翻译：电容式感应静电放电保护电路
公开(公告)号：US5173755A
公开(公告)日：1992-12-22
申请号：US711101
申请日：1991-06-03
申请人： Ramon Co , Kwok Fai V. Lee , Kenneth W. Ouyang
发明人： Ramon Co , Kwok Fai V. Lee , Kenneth W. Ouyang
IPC分类号： H01L27/02
CPC分类号： H01L27/0251
摘要： An integrated circuit electrostatic discharge (ESD) protection circuit employs a capacitor and a zener diode to trigger a thick oxide ESD shunt field effect transistor (FET). When an ESD induced voltage at an input or output node reaches the turn-on voltage determined by the zener diode breakdown voltage, the shunting transistor is turned on by current capacitively coupled to the base of the parasitic bipolar transistor inherently formed in the thick oxide FET. The parasitic bipolar transistor is turned on in its saturated mode, substantially shorting the node to ground. At the end of the ESD event when the ESD induced current is no longer sufficient to keep the shunting transistor in its saturated mode, the shunting transistor turns off and the ESD protection circuit returns to its off mode, monitoring the input or output node for the occurrence of another ESD event.
摘要翻译：集成电路静电放电（ESD）保护电路采用电容器和齐纳二极管来触发厚氧化物ESD分流场效应晶体管（FET）。当输入或输出节点处的ESD感应电压达到由齐纳二极管击穿电压确定的接通电压时，分流晶体管通过电容耦合到固有地形成在厚氧化物FET中的寄生双极晶体管的基极的电流导通。寄生双极晶体管在饱和模式下导通，实质上使节点接地短路。在静电放电事件结束时，ESD感应电流不足以使分流晶体管保持饱和模式，分流晶体管截止，ESD保护电路恢复到关闭模式，监视输入或输出节点发生另一个ESD事件。

2. 发明授权

US5162888A High DC breakdown voltage field effect transistor and integrated circuit 失效
标题翻译：高直流击穿电压场效应晶体管和集成电路
公开(公告)号：US5162888A
公开(公告)日：1992-11-10
申请号：US351669
申请日：1989-05-12
申请人： Ramon Co , Kenneth W. Ouyang , Jui C. Liang
发明人： Ramon Co , Kenneth W. Ouyang , Jui C. Liang
IPC分类号： H01L29/10 , H01L29/78
CPC分类号： H01L29/1045 , H01L29/7835
摘要： A field effect transistor device formed on an integrated circuit chip substrate and driven by the on-chip voltages having a well region formed in the substrate, and source and drain regions one of which is formed in the well region. The well region has a lower doping concentration than the source and drain regions and is of the same conductivity type. The well region provides a reduced electric field gradient at the source/substrate or drain/substrate junction and significantly increases the breakdown resistance of the device to DC voltages higher than the on-chip voltages. An input/output protection circuit employing the field effect transistor coupled in series between an integrated circuit output pad and the active devices on the chip providing ability to withstand coupling of the pad to a relatively high DC voltages.
摘要翻译：一种场效应晶体管器件，形成在集成电路芯片基板上，并由片上电压驱动，具有形成在衬底中的阱区，其中一个漏极区形成在阱区中。阱区具有比源区和漏区更低的掺杂浓度，并且具有相同的导电类型。阱区域在源极/衬底或漏极/衬底结点处提供减小的电场梯度，并且显着地将器件的耐击穿电压提高到高于片上电压的直流电压。使用串联耦合在集成电路输出焊盘和芯片上的有源器件之间的场效应晶体管的输入/输出保护电路提供了能够承受焊盘到相对高的DC电压的耦合的能力。

3. 发明申请

US20070164835A1 All-Digital Phase Modulator/Demodulator Using Multi-Phase Clocks and Digital PLL 有权
标题翻译：使用多相时钟和数字PLL的全数字相位调制器/解调器
公开(公告)号：US20070164835A1
公开(公告)日：2007-07-19
申请号：US11692472
申请日：2007-03-28
申请人： Ramon Co
发明人： Ramon Co
IPC分类号： H03C3/00
CPC分类号： H03L7/0814 , H03C3/0966 , H03L2207/50 , H04L27/22
摘要： Multi-phase clocks are used to encode and decode signals that are phase-modulated. The input signal is phase-compared with a feedback clock. Phase differences increment or decrement an up/down counter. The count value from the up/down counter is applied to a phase rotator, which selects one clock phase from a bank of multi-phase clocks. The multi-phase clocks have the same frequency, but are offset in phase from each other. An output divider divides the selected multi-phase clock to generate a phase-modulated output. A feedback divider divides a fixed-phase clock from the multi-phase clocks to generate the feedback clock. An analog or a digital front-end may be used to convert analog inputs to digital signals to increment or decrement the counter, or to encode multiple digital bits as phase assignments. For a de-modulator, a digital-to-analog converter (DAC) or a digital decoder produces the final output from the count of the up/down counter.
摘要翻译：多相时钟用于对相位调制的信号进行编码和解码。输入信号与反馈时钟进行相位比较。相位差递增或递减上/下计数器。来自递增/递减计数器的计数值被应用于从一组多相时钟选择一个时钟相位的相位旋转器。多相时钟具有相同的频率，但彼此相位偏移。输出分频器分频所选择的多相时钟以产生相位调制输出。反馈分频器将固定相位时钟与多相时钟分频，以产生反馈时钟。模拟或数字前端可以用于将模拟输入转换为数字信号，以递增或递减计数器，或将多个数字位编码为相位分配。对于解调器，数/模转换器（DAC）或数字解码器从上/下计数器的计数产生最终输出。

4. 发明申请

US20060282722A1 Loop-Back Memory-Module Extender Card for Self-Testing Fully-Buffered Memory Modules 有权
标题翻译：环回内存模块扩展卡，用于自检全缓冲内存模块
公开(公告)号：US20060282722A1
公开(公告)日：2006-12-14
申请号：US10908716
申请日：2005-05-24
申请人： Ramon Co , Tat Lai
发明人： Ramon Co , Tat Lai
IPC分类号： G01R31/28
CPC分类号： G11C29/56 , G11C5/04 , G11C2029/3602 , G11C2029/5602
摘要： A loop-back extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module under test. An Advanced Memory Buffer (AMB) on the memory module fully buffers DRAM chips on the memory module. The AMB inputs from and outputs to the test socket differential northbound lanes (toward a processor) and southbound lanes (away from the processor). The extender card has northbound loopback traces that connect northbound lane outputs from the memory module back to northbound-lane inputs to the memory module. Southbound loopback traces connect southbound lane outputs from the memory module back to southbound-lane inputs to the memory module. The loop-back extender card allows the AMB to perform loopback testing without modifying the PC motherboard. Series/shunt resistors can be placed on the loopback traces, or serpentine traces can be used to increase loopback delays.
摘要翻译：环回延长卡插入个人计算机（PC）主板上的内存模块插槽。扩展卡具有接收被测内存模块的测试插槽。存储器模块上的高级存储器缓冲器（AMB）完全缓冲存储器模块上的DRAM芯片。 AMB从测试插座差分北行车道（朝向处理器）和南行车道（远离处理器）输入和输出。扩展卡具有北向环回路线，将来自存储模块的北行车道输出连接回北行车道输入至存储模块。南向环回路线将内存模块的南行通道输出连接回内行模块的南行通道输入。环回延长卡允许AMB在不修改PC主板的情况下进行环回测试。串联/并联电阻可以放置在回送轨迹上，也可以使用蛇形轨迹来增加环回延迟。

5. 发明申请

US20060197546A1 Efficient Air-Flow Loop through Dual Burn-in Chambers with Removable Pattern-Generator Boards for Memory-Module Environmental Testing 有权
标题翻译：高效的气流回路通过双重烧录室与可拆卸图案发生器板进行内存模块环境测试
公开(公告)号：US20060197546A1
公开(公告)日：2006-09-07
申请号：US11306753
申请日：2006-01-10
申请人： Ramon Co , Tat Lai , David Sun
发明人： Ramon Co , Tat Lai , David Sun
IPC分类号： G01R31/02
CPC分类号： G01R31/2855 , G01R31/2863 , G01R31/31905 , G11C29/56 , G11C29/56004 , G11C29/56016 , G11C2029/2602
摘要： Two heat chambers are placed side-by-side. Heated air is blown upward through a first chamber and downward through a second heat chamber. An upper heating unit has a blower and heater that heat air exiting the first chamber and blows the heated air into the top of the second chamber. A lower heating unit has a blower and heater that heat air exiting the second chamber and blows the heated air into the top of the first chamber. Air is circulated in a loop through the two heat chambers by the two heating units. Inefficiencies from return pipes are eliminated by using the second chamber. The heated air is blown past memory modules under test in a heat chamber that has an insulated backplane. Pattern-generator cards outside the heat chamber exercise the memory modules and are cooled while memory modules in the heat chamber are heated.
摘要翻译：两个热室并排放置。加热空气向上穿过第一室并向下通过第二加热室。上加热单元具有鼓风机和加热器，其加热从第一室排出的空气并将加热的空气吹入第二室的顶部。下加热单元具有鼓风机和加热器，其加热从第二室排出的空气并将加热的空气吹入第一室的顶部。空气通过两个加热单元通过两个加热室循环循环。通过使用第二室来消除回流管的低效率。被加热的空气在具有绝缘背板的加热室中被吹过被测试的存储器模块。加热室外的图案发生器卡锻炼存储器模块，并在加热室中的存储器模块被加热时被冷却。

6. 发明申请

US20050246594A1 Extender Card for Testing Error-Correction-Code (ECC) Storage Area on Memory Modules 有权
标题翻译：扩展卡用于测试内存模块上的错误纠正代码（ECC）存储区域
公开(公告)号：US20050246594A1
公开(公告)日：2005-11-03
申请号：US10709156
申请日：2004-04-16
申请人： Ramon Co , Tat Lai , David Sun
发明人： Ramon Co , Tat Lai , David Sun
IPC分类号： G06F11/00 , G06F11/267 , G11C29/24
CPC分类号： G11C29/24 , G06F11/2215 , G11C5/04 , G11C2029/5602
摘要： Memory modules with an extra dynamic-random-access memory (DRAM) chip for storing error-correction code (ECC) are tested on a personal computer (PC) motherboard tester using a cross-over extender card inserted into a memory module socket on the motherboard. ECC code generated on the motherboard is normally stored in the extra ECC DRAM chip, preventing test patterns such as checkerboards and walking-ones to be written directly to the ECC DRAM chip. During testing, the cross-over extender card routes signals from the motherboard for one of the data DRAM chips to the ECC DRAM chip, while the ECC code is routed to one of the data DRAM chips. The checkerboard or other test pattern is thus written and read from the ECC DRAM chip that normally stores the ECC code. The cross-over extender card can be hardwired, or can have a switch to allow normal operation or testing of the ECC DRAM chip.
摘要翻译：具有用于存储纠错码（ECC）的额外动态随机存取存储器（DRAM）芯片的存储器模块在个人计算机（PC）主板测试器上使用插入到内存模块插槽中的跨越延长卡进行测试母板。在主板上产生的ECC代码通常存储在额外的ECC DRAM芯片中，防止诸如棋盘和步行的测试图案直接写入ECC DRAM芯片。在测试期间，交叉扩展卡将来自主板的信号从数据DRAM芯片中的一个传送到ECC DRAM芯片，而ECC代码被路由到数据DRAM芯片之一。因此，棋盘或其他测试图案由通常存储ECC代码的ECC DRAM芯片写入和读出。交叉扩展卡可以是硬连线的，或者可以有开关来允许ECC DRAM芯片的正常操作或测试。

7. 发明申请

US20050125712A1 Manifold-Distributed Air Flow Over Removable Test Boards in a Memory-Module Burn-In System With Heat Chamber Isolated by Backplane 有权
标题翻译：通过背板隔离的热室的内存模块烧录系统中的可拆卸测试板上的歧管分布式气流
公开(公告)号：US20050125712A1
公开(公告)日：2005-06-09
申请号：US10906318
申请日：2005-02-14
申请人： Ramon Co , Tat Lai , David Sun
发明人： Ramon Co , Tat Lai , David Sun
IPC分类号： G01R31/28 , G01R31/319 , G11C29/56 , G11C29/00 , G01R31/02
CPC分类号： G01R31/2855 , G01R31/2863 , G01R31/31905 , G11C29/56 , G11C29/56004 , G11C29/56016 , G11C2029/2602
摘要： Hot air blown past memory modules under test in a heat chamber is improved. Hot air entering the chamber from an inlet pipe is split by a manifold and deflectors. Holes in the manifold allow for a relatively even air distribution within the chamber, minimizing temperature variations. Return air is collected by a heat-chamber bottom cover into a return pipe. A heating unit re-heats the return air and blows it into the inlet pipe. One side of the heat chamber is an insulated backplane. Memory modules are inserted into sockets on module motherboards, which are inserted into motherboard sockets on the backplane. On the other side of the backplane, card sockets receive pattern-generator cards outside the heat chamber but electrically connected to the module motherboards through the backplane. The pattern-generator cards exercise the memory modules. The pattern-generator cards are cooled while memory modules in the heat chamber are heated.
摘要翻译：改进了在热室中被测试的存储器模块的热空气。从入口管进入腔室的热空气被歧管和导流器分开。歧管中的孔允许室内相对均匀的空气分布，使温度变化最小化。返回空气由热室底盖收集回流管。加热单元重新加热回流空气并将其吹入入口管。加热室的一侧是绝缘背板。内存模块插入模块主板上的插座，插入背板主板插槽。在背板的另一侧，卡插座在加热室外部接收图案发生器卡，但通过背板电连接到模块主板。图案发生器卡练习内存模块。图案发生器卡被冷却，而加热室中的存储器模块被加热。

8. 发明授权

US5550515A Multiphase clock synthesizer having a plurality of phase shifted inputs to a plurality of phase comparators in a phase locked loop 失效
标题翻译：多相时钟合成器具有在锁相环中的多个相位比较器的多个相移输入
公开(公告)号：US5550515A
公开(公告)日：1996-08-27
申请号：US378798
申请日：1995-01-27
申请人： Jui Liang , Ramon Co , Ann Gui
发明人： Jui Liang , Ramon Co , Ann Gui
IPC分类号： H03L7/07 , H03L7/087 , H03L7/089 , H03L7/099 , H03L7/191 , H03L7/18
CPC分类号： H03L7/087 , H03L7/07 , H03L7/0995 , H03L7/191 , H03L7/0891
摘要： A phase-locked loop wherein the output signal is effectively sampled at an increased rate from conventional phase-locked loops, allowing for a greater increase in the ratio of the output frequency to the input frequency while reducing the possibility of jitter or failure to lock. Multiple differently phased reference signals and correspondingly phased feedback signals are produced. The comparison of the feedback signals and the reference signals produce multiple error signals which are combined to adjust the oscillation frequency of the voltage-controlled oscillator.
摘要翻译：一种锁相环，其中输出信号以常规锁相环的增加速率被有效地采样，从而允许输出频率与输入频率的比例更大的增加，同时减少抖动或不能锁定的可能性。产生多个不同相位的参考信号和相应的相位反馈信号。反馈信号和参考信号的比较产生多个误差信号，这些信号被组合以调节压控振荡器的振荡频率。

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