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1. 发明授权

US07032082B1 Centralized memory allocation with write pointer drift correction 有权
标题翻译：集中存储器分配与写指针漂移校正
公开(公告)号：US07032082B1
公开(公告)日：2006-04-18
申请号：US09942623
申请日：2001-08-31
申请人： Rami Rahim , Pradeep Sindhu , Raymond Marcelino Manese Lim , Sreeram Veeragandham , David Skinner
发明人： Rami Rahim , Pradeep Sindhu , Raymond Marcelino Manese Lim , Sreeram Veeragandham , David Skinner
IPC分类号： G06F12/06 , G06F13/16
CPC分类号： G06F12/0684 , G06F12/02 , G06F12/0813
摘要： A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a threshold amount. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.
摘要翻译：用于写入数据的系统包括存储器，至少一个存储器控制器和控制逻辑。内存存储数据单元。存储器控制器接收与数据单元相关联的写请求，并将数据单元存储在存储器中。存储器控制器还发送包括存储数据单元的地址的应答。控制逻辑接收答复并确定答复中的地址是否与包含在与其他存储器控制器相关联的应答中的地址相差阈值。当这种情况发生时，控制逻辑执行纠正措施以使与存储器控制器相关联的地址返回到定义的范围内。

2. 发明授权

US08089861B1 Data verification using signature 有权
标题翻译：使用签名数据验证
公开(公告)号：US08089861B1
公开(公告)日：2012-01-03
申请号：US12143064
申请日：2008-06-20
申请人： Rami Rahim , Pradeep Sindhu
发明人： Rami Rahim , Pradeep Sindhu
IPC分类号： H04L9/30
CPC分类号： H04L63/123
摘要： A system processes packets in a network device and includes a memory for buffering the packets. The memory may store the packets in memory in data cells. To expedite packet processing, portions of the packet are extracted and placed in a notification, which is then used for packet processing operations, such as route lookup, policing, and accounting. The notification may also include address elements, such as address offsets, that define the locations of the data cells in memory. The address elements can be used to read the data cells from the memory when packet processing is done. If the notification cannot hold all the address elements, additional cells, indirect cells, are created for holding the remaining address elements. The indirect cells are formed in a linked list. The notification contains an address element. To prevent reading incorrect indirect cells, each indirect cell is written with a signature that is created based on the notification. When an indirect cell is read out, the signature is checked to determine whether it belongs to that notification. If the signature is not correct, this may mean that the indirect cell has not yet been written to memory, or that the indirect cell was in some way corrupted during writing, storing, or reading.
摘要翻译：系统处理网络设备中的分组，并且包括用于缓冲分组的存储器。存储器可以将数据包存储在数据单元中。为了加快分组处理，分组的部分被提取并放置在通知中，然后用于诸如路由查找，管理和计费之类的分组处理操作。通知还可以包括定义存储器中的数据单元的位置的地址元素，例如地址偏移。当数据包处理完成时，地址元素可用于从存储器读取数据单元。如果通知不能容纳所有地址元素，则创建附加单元格，间接单元格以保留剩余的地址单元。间接细胞在链表中形成。通知包含地址元素。为了防止读取不正确的间接单元格，每个间接单元都将使用基于通知创建的签名进行写入。当读取间接单元时，检查签名以确定它是否属于该通知。如果签名不正确，这可能意味着间接单元格尚未写入存储器，或间接单元格在写入，存储或读取期间以某种方式损坏。

3. 发明授权

US07421564B1 Incrementing successive write operations to a plurality of memory devices 有权
标题翻译：将连续的写入操作递增到多个存储器件
公开(公告)号：US07421564B1
公开(公告)日：2008-09-02
申请号：US11356150
申请日：2006-02-17
申请人： Rami Rahim , Pradeep Sindhu , Raymond Marcelino Manese Lim , Sreeram Veeragandham , David Skinner
发明人： Rami Rahim , Pradeep Sindhu , Raymond Marcelino Manese Lim , Sreeram Veeragandham , David Skinner
IPC分类号： G06F12/06
CPC分类号： G06F12/0684 , G06F12/02 , G06F12/0813
摘要： A centralized memory allocation system utilizes write pointer drift correction. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a given address range. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.
摘要翻译：集中式存储器分配系统利用写指针漂移校正。内存存储数据单元。存储器控制器接收与数据单元相关联的写请求，并将数据单元存储在存储器中。存储器控制器还发送包括存储数据单元的地址的应答。控制逻辑接收答复，并确定答复中的地址是否与给定地址范围与其他存储器控制器相关的回复中包含的地址不同。当这种情况发生时，控制逻辑执行纠正措施以使与存储器控制器相关联的地址返回到定义的范围内。

4. 发明授权

US07039774B1 Memory allocation using a memory address pool 失效
标题翻译：使用内存地址池进行内存分配
公开(公告)号：US07039774B1
公开(公告)日：2006-05-02
申请号：US10062424
申请日：2002-02-05
申请人： Jorge Cruz-Rios , Rami Rahim , Venkateswarlu Talapaneni , Pradeep Sindhu
发明人： Jorge Cruz-Rios , Rami Rahim , Venkateswarlu Talapaneni , Pradeep Sindhu
IPC分类号： G06F12/00
CPC分类号： G06F12/023
摘要： A system for managing memory includes a memory and a memory allocation unit. The memory stores a pool of memory addresses for writing data to the memory and stores a counter value. The memory allocation unit retrieves memory addresses from the pool in response to write requests from data sources. The memory allocation unit further replenishes the memory addresses in the pool when the pool is emptied and increments the counter value in response to each replenishment of the memory addresses in the pool.
摘要翻译：用于管理存储器的系统包括存储器和存储器分配单元。存储器存储用于将数据写入存储器的存储器地址池并存储计数器值。内存分配单元响应于来自数据源的写入请求从池中检索存储器地址。当池被清空时，存储器分配单元进一步补充池中的存储器地址，并响应于池中的存储器地址的每次补充递增计数器值。

5. 发明授权

US08880808B1 Centralized memory allocation with write pointer drift correction 有权
标题翻译：集中存储器分配与写指针漂移校正
公开(公告)号：US08880808B1
公开(公告)日：2014-11-04
申请号：US12181930
申请日：2008-07-29
申请人： Rami Rahim , Pradeep Sindhu , Raymond Marcelino Manese Lim , Sreeram Veeragandham , David Skinner
发明人： Rami Rahim , Pradeep Sindhu , Raymond Marcelino Manese Lim , Sreeram Veeragandham , David Skinner
IPC分类号： G06F12/06 , G06F12/02
CPC分类号： G06F12/0684 , G06F12/02 , G06F12/0813
摘要： A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a threshold amount. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.
摘要翻译：用于写入数据的系统包括存储器，至少一个存储器控制器和控制逻辑。内存存储数据单元。存储器控制器接收与数据单元相关联的写请求，并将数据单元存储在存储器中。存储器控制器还发送包括存储数据单元的地址的应答。控制逻辑接收答复并确定答复中的地址是否与包含在与其他存储器控制器相关联的应答中的地址相差阈值。当这种情况发生时，控制逻辑执行纠正措施以使与存储器控制器相关联的地址返回到定义的范围内。

6. 发明授权

US07171530B1 Memory allocation using a memory address pool 失效
标题翻译：使用内存地址池进行内存分配
公开(公告)号：US07171530B1
公开(公告)日：2007-01-30
申请号：US11366386
申请日：2006-03-03
申请人： Jorge Cruz-Rios , Rami Rahim , Venkateswarlu Talapaneni , Pradeep Sindhu
发明人： Jorge Cruz-Rios , Rami Rahim , Venkateswarlu Talapaneni , Pradeep Sindhu
IPC分类号： G06F12/00
CPC分类号： G06F12/023
摘要： A system maintains a first counter value that indicates a number of times memory addresses in a memory address pool have been replenished. The system further maintains a second counter value that indicates a number of times a circular buffer has been filled with memory addresses retrieved from the memory address pool. The system ages memory addresses allocated to memory write requests based on the first and second counter values.
摘要翻译：系统维护指示存储器地址池中的存储器地址已经被补充的次数的第一计数器值。系统进一步维护第二计数器值，其指示循环缓冲器已经被从存储器地址池检索的存储器地址填充的次数。系统基于第一和第二计数器值来分配分配给存储器写入请求的存储器地址。

7. 发明授权

US07406089B1 Data verification using signature 有权
标题翻译：使用签名数据验证
公开(公告)号：US07406089B1
公开(公告)日：2008-07-29
申请号：US10210511
申请日：2002-07-31
申请人： Rami Rahim , Pradeep Sindhu
发明人： Rami Rahim , Pradeep Sindhu
IPC分类号： H04L9/30
CPC分类号： H04L63/123
摘要： A system processes packets in a network device and includes a memory for buffering the packets. The memory may store the packets in memory in data cells. To expedite packet processing, portions of the packet are extracted and placed in a notification, which is then used for packet processing operations, such as route lookup, policing, and accounting. The notification may also include address elements, such as address offsets, that define the locations of the data cells in memory. The address elements can be used to read the data cells from the memory when packet processing is done. If the notification cannot hold all the address elements, additional cells, indirect cells, are created for holding the remaining address elements. The indirect cells are formed in a linked list. The notification contains an address element. To prevent reading incorrect indirect cells, each indirect cell is written with a signature that is created based on the notification. When an indirect cell is read out, the signature is checked to determine whether it belongs to that notification. If the signature is not correct, this may mean that the indirect cell has not yet been written to memory, or that the indirect cell was in some way corrupted during writing, storing, or reading.
摘要翻译：系统处理网络设备中的分组，并且包括用于缓冲分组的存储器。存储器可以将数据包存储在数据单元中。为了加快分组处理，分组的部分被提取并放置在通知中，然后用于诸如路由查找，管理和计费之类的分组处理操作。通知还可以包括定义存储器中的数据单元的位置的地址元素，例如地址偏移。当数据包处理完成时，地址元素可用于从存储器读取数据单元。如果通知不能容纳所有地址元素，则创建附加单元格，间接单元格以保留剩余的地址单元。间接细胞在链表中形成。通知包含地址元素。为了防止读取不正确的间接单元格，每个间接单元都将使用基于通知创建的签名进行写入。当读取间接单元时，检查签名以确定它是否属于该通知。如果签名不正确，这可能意味着间接单元格尚未写入存储器，或间接单元格在写入，存储或读取期间以某种方式损坏。

8. 发明授权

US09112786B2 Systems and methods for selectively performing explicit congestion notification 有权
标题翻译：选择性地执行显式拥塞通知的系统和方法
公开(公告)号：US09112786B2
公开(公告)日：2015-08-18
申请号：US13902463
申请日：2013-05-24
申请人： Pradeep Sindhu , Debashis Basu , Jayabharat Boddu , Avanindra Godbole
发明人： Pradeep Sindhu , Debashis Basu , Jayabharat Boddu , Avanindra Godbole
IPC分类号： G01R31/08 , H04L12/801 , H04L12/835 , H04L12/823
CPC分类号： H04L47/12 , H04L47/10 , H04L47/11 , H04L47/29 , H04L47/30 , H04L47/32 , H04L47/35
摘要： A system provides congestion control and includes multiple queues that temporarily store data and a drop engine. The system associates a value with each of the queues, where each of the values relates to an amount of memory associated with the queue. The drop engine compares the value associated with a particular one of the queues to one or more programmable thresholds and selectively performs explicit congestion notification or packet dropping on data in the particular queue based on a result of the comparison.
摘要翻译：系统提供拥塞控制，并且包括临时存储数据的多个队列和丢弃引擎。该系统将值与每个队列相关联，其中每个值与与队列相关联的内存量相关。丢包引擎将与特定队列相关联的值与一个或多个可编程阈值进行比较，并且基于比较的结果选择性地对特定队列中的数据进行显式拥塞通知或分组丢弃。

9. 发明授权

US08880856B1 Efficient arithmetic logic units 有权
标题翻译：高效的算术逻辑单元
公开(公告)号：US08880856B1
公开(公告)日：2014-11-04
申请号：US12486114
申请日：2009-06-17
申请人： Jean-Marc Frailong , Pradeep Sindhu , Jeffrey G. Libby , Jian Hui Huang , Rajesh Nair , John Keen
发明人： Jean-Marc Frailong , Pradeep Sindhu , Jeffrey G. Libby , Jian Hui Huang , Rajesh Nair , John Keen
IPC分类号： G06F15/00
CPC分类号： G06F9/28 , G06F7/57 , G06F9/30 , G06F9/3001 , G06F9/30018 , G06F9/30072 , G06F9/30145 , G06F9/3859 , G06F9/3893 , G06F15/00
摘要： A processor may include a conditional arithmetic logic unit and a main arithmetic logic unit. The conditional arithmetic logic unit may perform a first arithmetic logic operation to generate a first result, and output the result. The main arithmetic logic unit may select input buses among a plurality of data buses that carry the first result from the conditional arithmetic logic unit, perform a second arithmetic logic operation on data provided by the selected input buses to generate a second result, and write the second result in a storage component.
摘要翻译：处理器可以包括条件算术逻辑单元和主算术逻辑单元。条件算术逻辑单元可以执行第一算术逻辑运算以产生第一结果，并输出结果。主算术逻辑单元可以选择携带来自条件算术逻辑单元的第一结果的多个数据总线中的输入总线，对由所选择的输入总线提供的数据执行第二运算逻辑运算以产生第二结果，并写入第二个结果是存储组件。

10. 发明授权

US08605722B1 Deadlock-resistant fabric tree replication in a network device 有权
公开(公告)号：US08605722B1
公开(公告)日：2013-12-10
申请号：US12759850
申请日：2010-04-14
申请人： Pradeep Sindhu , Jean-Marc Frailong , Sarin Thomas , Srihari Vegesna , David J. Ofelt , Chang-Hong Wu
发明人： Pradeep Sindhu , Jean-Marc Frailong , Sarin Thomas , Srihari Vegesna , David J. Ofelt , Chang-Hong Wu
IPC分类号： H04L12/28
CPC分类号： H04L45/16 , H04L12/1863 , H04L49/201 , H04L49/90 , H04L67/1095
摘要： In general, the invention is directed to techniques for reducing deadlocks that may arise when performing fabric replication. For example, as described herein, a network device includes packet replicators that each comprises a plurality of resource partitions. A replication data structure for a packet received by the network device includes packet replicator nodes that are arranged hierarchically to occupy one or more levels of the replication data structure. Each of the resource partitions in each of the plurality of packet replicators is associated with a different level of the replication data structure. The packet replicators replicate the packet according to the replication data structure, and each of the packet replicators handles the packet using the one of the resource partitions of the packet replicator that is associated with the level of the replication data structure occupied by the node that corresponds to that particular packet replicator.

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