专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090152626A1 Super Halo Formation Using a Reverse Flow for Halo Implants 审中-公开
标题翻译：超光晕使用反向流动为光晕植入物
公开(公告)号：US20090152626A1
公开(公告)日：2009-06-18
申请号：US11959032
申请日：2007-12-18
申请人： Ramesh Venugopal , Srinivasan Chakravarthi , Chris Bowen
发明人： Ramesh Venugopal , Srinivasan Chakravarthi , Chris Bowen
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814
摘要： Shrinking dimensions of MOS transistors in integrated circuits requires tighter distributions of dopants in pocket regions from halo ion implant processes. In conventional fabrication process sequences, halo dopant distributions spread during source/drain anneals. The instant invention is a method of fabricating MOS transistors in an integrated circuit in which halo ion are performed after source/drain anneals. In the inventive method, source/drain spacers on MOS gate sidewalls are removed prior to halo ion implant processes. Spacers to offset metal silicide are formed after halo implants and may be of low-k dielectric material to reduce gate to drain capacitance. A compressive stress layer may be deposited on MOS gates after source/drain spacers are removed for greater stress transfer efficiency to the MOS gates. An integrated circuit embodying the inventive method is also disclosed.
摘要翻译：集成电路中MOS晶体管的收缩尺寸需要从光晕离子注入工艺在口袋区域中更严格地分配掺杂剂。在常规制造工艺序列中，卤素掺杂剂分布在源极/漏极退火期间扩散。本发明是在源极/漏极退火之后执行卤素离子的集成电路中制造MOS晶体管的方法。在本发明的方法中，在卤素离子注入工艺之前，MOS栅极侧壁上的源极/漏极间隔物被去除。偏移金属硅化物的间隔物在晕轮植入物之后形成，并且可以是低k电介质材料以减小栅极至漏极电容。在源极/漏极间隔物被去除之后，压电应力层可以沉积在MOS栅极上，以提高MOS栅极的应力传递效率。还公开了体现本发明方法的集成电路。

2. 发明授权

US08435849B2 Method of forming a CMOS IC having a compressively stressed metal layer in the NMOS area 有权
标题翻译：在NMOS区域中形成具有压应力金属层的CMOS IC的方法
公开(公告)号：US08435849B2
公开(公告)日：2013-05-07
申请号：US13440344
申请日：2012-04-05
申请人： Xin Wang , Zhiqiang Wu , Ramesh Venugopal
发明人： Xin Wang , Zhiqiang Wu , Ramesh Venugopal
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28052 , H01L21/823842 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845 , H01L29/7847
摘要： A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type polysilicon to establish a desired work function in the gate, layer of compressively stressed metal, and a third layer of polysilicon to provide a silicon surface for subsequent formation of metal silicide. Candidates for the compressively stressed metal are TiN, TaN, W, and Mo. In a CMOS IC, the n-type polysilicon layer and metal layer are patterned in NMOS transistor areas, while the first polysilicon layer and third polysilicon layer are patterned in both NMOS and PMOS transistor areas. Polysilicon CMP may be used to reduce topography between the NMOS and PMOS gate stacks to facilitate gate pattern photolithography.
摘要翻译：公开了用于在NMOS沟道中引起拉伸应力的IC中的NMOS晶体管的栅极堆叠。栅极堆叠包括第一层未掺杂的多晶硅，第二层n型多晶硅，以在栅极中建立所需的功函数，压缩应力金属层，以及第三层多晶硅，以提供硅表面，用于随后形成金属硅化物。用于压应力金属的候选物是TiN，TaN，W和Mo。在CMOS IC中，n型多晶硅层和金属层在NMOS晶体管区域中被图案化，而第一多晶硅层和第三多晶硅层被图案化 NMOS和PMOS晶体管区域。多晶硅CMP可以用于减小NMOS和PMOS栅极堆叠之间的形貌，以便于栅极图案光刻。

3. 发明申请

US20080272442A1 N+ POLY ON HIGH-K DIELECTRIC FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译： N + POLY ON HIGH-K介电用于半导体器件
公开(公告)号：US20080272442A1
公开(公告)日：2008-11-06
申请号：US12137674
申请日：2008-06-12
申请人： Ramesh Venugopal , Christoph Wasshuber , David Barry Scott
发明人： Ramesh Venugopal , Christoph Wasshuber , David Barry Scott
IPC分类号： H01L29/78
CPC分类号： H01L29/7838 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823857 , H01L29/517
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).
摘要翻译：本发明通过提供采用高k电介质层的制造方法来促进半导体制造。 n型阱区（304）形成在半导体本体（302）内。通过将p型掺杂剂注入到n型阱区域中以形成反掺杂区域（307）来执行阈值电压调整注入。在器件（300）上形成高k电介质层（308）。在高k电介质层上形成多晶硅层（310），并掺杂n型。图案化高k电介质层（308）和多晶硅层（310）以形成多晶硅栅极结构。 P型源极/漏极区（306）形成在n型阱区（304）内。

4. 发明申请

US20060223248A1 N+ poly on high-k dielectric for semiconductor devices 有权
标题翻译：用于半导体器件的高k电介质上的N + poly
公开(公告)号：US20060223248A1
公开(公告)日：2006-10-05
申请号：US11091989
申请日：2005-03-29
申请人： Ramesh Venugopal , Christoph Wasshuber , David Scott
发明人： Ramesh Venugopal , Christoph Wasshuber , David Scott
IPC分类号： H01L21/336
CPC分类号： H01L29/7838 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823857 , H01L29/517
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).
摘要翻译：本发明通过提供采用高k电介质层的制造方法来促进半导体制造。 n型阱区（304）形成在半导体本体（302）内。通过将p型掺杂剂注入到n型阱区域中以形成反掺杂区域（307）来执行阈值电压调整注入。在器件（300）上形成高k电介质层（308）。在高k电介质层上形成多晶硅层（310），并掺杂n型。图案化高k电介质层（308）和多晶硅层（310）以形成多晶硅栅极结构。 P型源极/漏极区（306）形成在n型阱区（304）内。

5. 发明授权

US07407850B2 N+ poly on high-k dielectric for semiconductor devices 有权
标题翻译：用于半导体器件的高k电介质上的N + poly
公开(公告)号：US07407850B2
公开(公告)日：2008-08-05
申请号：US11091989
申请日：2005-03-29
申请人： Ramesh Venugopal , Christoph Wasshuber , David Barry Scott
发明人： Ramesh Venugopal , Christoph Wasshuber , David Barry Scott
IPC分类号： H01L21/8238
CPC分类号： H01L29/7838 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823857 , H01L29/517
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).
摘要翻译：本发明通过提供采用高k电介质层的制造方法来促进半导体制造。 n型阱区（304）形成在半导体本体（302）内。通过将p型掺杂剂注入到n型阱区域中以形成反掺杂区域（307）来执行阈值电压调整注入。在器件（300）上形成高k电介质层（308）。在高k电介质层上形成多晶硅层（310），并掺杂n型。图案化高k电介质层（308）和多晶硅层（310）以形成多晶硅栅极结构。 P型源极/漏极区（306）形成在n型阱区（304）内。

6. 发明授权

US07208379B2 Pitch multiplication process 有权
标题翻译：间距倍增过程
公开(公告)号：US07208379B2
公开(公告)日：2007-04-24
申请号：US10997936
申请日：2004-11-29
申请人： Ramesh Venugopal , Christoph Wasshuber
发明人： Ramesh Venugopal , Christoph Wasshuber
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L29/045 , H01L29/0657 , H01L29/1037 , H01L29/4236 , H01L29/78 , H01L29/78696 , H01L29/808 , H01L29/8086
摘要： A method for multiplying the pitch of a semiconductor device is disclosed. The method includes forming a patterned mask layer on a first layer, where the patterned mask layer has a first line width. The first layer can then be etched to form a first plurality of sloped sidewalls. After removing a portion of the patterned mask so that the patterned mask layer has a second line width less than the first line width, the first layer can be etched again to form a second plurality of sloped sidewalls. The patterned mask layer can then be removed. The first layer can be etched again to form a third plurality of sloped sidewalls. The first plurality of sloped sidewalls, the second plurality of sloped sidewalls, and the third plurality of sloped sidewalls can form an array of parallel triangular channels.
摘要翻译：公开了一种用于乘以半导体器件的间距的方法。该方法包括在第一层上形成图案化掩模层，其中图案化掩模层具有第一线宽度。然后可以蚀刻第一层以形成第一多个倾斜的侧壁。在去除图案化掩模的一部分以使得图案化掩模层具有小于第一线宽度的第二线宽度之后，可以再次蚀刻第一层以形成第二多个倾斜侧壁。然后可以去除图案化的掩模层。可以再次蚀刻第一层以形成第三多个倾斜的侧壁。第一多个倾斜侧壁，第二多个倾斜侧壁和第三多个倾斜侧壁可以形成平行三角形通道的阵列。

7. 发明申请

US20120190158A1 NMOS TRANSISTOR WITH ENHANCED STRESS GATE 有权
标题翻译：具有增强应力栅的NMOS晶体管
公开(公告)号：US20120190158A1
公开(公告)日：2012-07-26
申请号：US13440344
申请日：2012-04-05
申请人： Xin Wang , Zhiqiang Wu , Ramesh Venugopal
发明人： Xin Wang , Zhiqiang Wu , Ramesh Venugopal
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28052 , H01L21/823842 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845 , H01L29/7847
摘要： A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type polysilicon to establish a desired work function in the gate, layer of compressively stressed metal, and a third layer of polysilicon to provide a silicon surface for subsequent formation of metal silicide. Candidates for the compressively stressed metal are TiN, TaN, W, and Mo. In a CMOS IC, the n-type polysilicon layer and metal layer are patterned in NMOS transistor areas, while the first polysilicon layer and third polysilicon layer are patterned in both NMOS and PMOS transistor areas. Polysilicon CMP may be used to reduce topography between the NMOS and PMOS gate stacks to facilitate gate pattern photolithography.
摘要翻译：公开了用于在NMOS沟道中引起拉伸应力的IC中的NMOS晶体管的栅极堆叠。栅极堆叠包括第一层未掺杂的多晶硅，第二层n型多晶硅，以在栅极中建立所需的功函数，压缩应力金属层，以及第三层多晶硅，以提供硅表面，用于随后形成金属硅化物。用于压应力金属的候选物是TiN，TaN，W和Mo。在CMOS IC中，n型多晶硅层和金属层在NMOS晶体管区域中被图案化，而第一多晶硅层和第三多晶硅层被图案化 NMOS和PMOS晶体管区域。多晶硅CMP可以用于减小NMOS和PMOS栅极堆叠之间的形貌，以便于栅极图案光刻。

8. 发明申请

US20060113636A1 Novel pitch multiplication process 有权
标题翻译：新的音调乘法过程
公开(公告)号：US20060113636A1
公开(公告)日：2006-06-01
申请号：US10997936
申请日：2004-11-29
申请人： Ramesh Venugopal , Christoph Wasshuber
发明人： Ramesh Venugopal , Christoph Wasshuber
IPC分类号： H01L29/06 , H01L21/467
CPC分类号： H01L21/28123 , H01L29/045 , H01L29/0657 , H01L29/1037 , H01L29/4236 , H01L29/78 , H01L29/78696 , H01L29/808 , H01L29/8086
摘要： A method for multiplying the pitch of a semiconductor device is disclosed. The method includes forming a patterned mask layer on a first layer, where the patterned mask layer has a first line width. The first layer can then be etched to form a first plurality of sloped sidewalls. After removing a portion of the patterned mask so that the patterned mask layer has a second line width less than the first line width, the first layer can be etched again to form a second plurality of sloped sidewalls. The patterned mask layer can then be removed. The first layer can be etched again to form a third plurality of sloped sidewalls. The first plurality of sloped sidewalls, the second plurality of sloped sidewalls, and the third plurality of sloped sidewalls can form an array of parallel triangular channels.
摘要翻译：公开了一种用于乘以半导体器件的间距的方法。该方法包括在第一层上形成图案化掩模层，其中图案化掩模层具有第一线宽度。然后可以蚀刻第一层以形成第一多个倾斜的侧壁。在去除图案化掩模的一部分以使得图案化掩模层具有小于第一线宽度的第二线宽度之后，可以再次蚀刻第一层以形成第二多个倾斜侧壁。然后可以去除图案化的掩模层。可以再次蚀刻第一层以形成第三多个倾斜的侧壁。第一多个倾斜侧壁，第二多个倾斜侧壁和第三多个倾斜侧壁可以形成平行三角形通道的阵列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式