专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6058472A Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine 失效
标题翻译：用于维持程序正确性，同时允许在无序机器中经过存储器加载负载的装置
公开(公告)号：US6058472A
公开(公告)日：2000-05-02
申请号：US882311
申请日：1997-06-25
申请人： Ramesh Panwar , P.K. Chidambaran , Ricky C. Hetherington
发明人： Ramesh Panwar , P.K. Chidambaran , Ricky C. Hetherington
IPC分类号： G06F9/38
CPC分类号： G06F9/3834 , G06F9/3861
摘要： A system, apparatus and method for ensuring program correctness in an out-of-order processor spite of younger load instructions being boosted past an older store utilizing a memory disambiguation buffer ("MDB"). The memory disambiguation buffer stores all memory operations that have not yet been retired. Each entry has several fields amongst which are the data and the addresses of the memory operations. An incoming load checks its address against the addresses of all the stores. If there is a match against an older store, then the load must have received old data from the data cache and the load operation is replayed to seek data from the memory disambiguation buffer on the replay. If on the other hand, there were no matches on any older store, the load is assumed to have received the right data from the data cache (assuming a data cache hit). An incoming store checks its address against the addresses of all younger loads. If there is a match against any younger load, then the younger load is replayed along with all of its dependents.
摘要翻译：一种用于确保无序处理器中的程序正确性的系统，装置和方法，尽管较小的加载指令通过使用存储器消歧缓冲器（“MDB”）的较旧存储器被提升。内存消歧缓冲区存储所有尚未被停用的内存操作。每个条目都有几个字段，其中包括数据和内存操作的地址。传入的负载根据所有商店的地址检查其地址。如果与较旧的存储器进行匹配，则加载必须已经从数据高速缓存中接收到旧数据，并且重播加载操作以从重放的内存消歧缓冲区中寻找数据。如果另一方面，任何旧的存储都没有匹配，假设负载从数据高速缓存中接收到正确的数据（假设数据缓存命中）。传入商店根据所有年轻人的地址检查其地址。如果与任何较小的负载相匹配，那么年轻的负载与其所有的家属一起重播。

2. 发明授权

US5948106A System for thermal overload detection and prevention for an integrated circuit processor 失效
标题翻译：用于集成电路处理器的热过载检测和防止系统
公开(公告)号：US5948106A
公开(公告)日：1999-09-07
申请号：US882613
申请日：1997-06-25
申请人： Ricky C. Hetherington , Ramesh Panwar
发明人： Ricky C. Hetherington , Ramesh Panwar
IPC分类号： G06F1/20 , G06F15/00
CPC分类号： G06F1/206
摘要： A system and method for thermal overload detection and protection for a processor which allows the processor to run at near maximum potential for the vast majority of its execution life. This is effectuated by the provision of circuitry to detect when the processor has exceeded its thermal thresholds and which then causes the processor to automatically reduce the clock rate to a fraction of the nominal clock while execution continues. When the thermal condition has stabilized, the clock may be raised in a stepwise fashion back to the nominal clock rate. Throughout the period of cycling the clock frequency from nominal to minimum and back, the program continues to be executed. Also provided is a queue activity rise time detector and method to control the rate of acceleration of a functional unit from idle to full throttle by a localized stall mechanism at the boundary of each stage in the pipe. This mechanism can detect when an idle queue is suddenly overwhelmed with input such that over a short period of approximately 10-20 machine cycles, the queue activity rate has increased from idle to near stall threshold.
摘要翻译：一种用于处理器的热过载检测和保护的系统和方法，其允许处理器在其绝大多数执行寿命期间以接近最大潜力运行。这通过提供电路来检测何时处理器已经超过其热阈值并且然后使处理器在执行继续时自动将时钟速率降低到标称时钟的一小部分来实现。当热条件稳定时，时钟可以逐步升高回到标称时钟速率。在将时钟频率从标称到最小和反向的整个周期期间，程序继续执行。还提供了一种队列活动上升时间检测器和方法，用于通过在管道中的每个阶段的边界处的局部失速机构来控制功能单元从怠速到全节气门的加速率。这种机制可以检测空闲队列何时突然被输入压倒，使得在大约10-20个机器周期的短时间内，队列活动速率已经从空闲增加到接近失速阈值。

3. 发明授权

US5890008A Method for dynamically reconfiguring a processor 失效
标题翻译：一种用于动态重新配置处理器的方法
公开(公告)号：US5890008A
公开(公告)日：1999-03-30
申请号：US882171
申请日：1997-06-25
申请人： Ramesh Panwar , Ricky C. Hetherington
发明人： Ramesh Panwar , Ricky C. Hetherington
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3855 , G06F9/3806 , G06F9/382 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/3877
摘要： A method and apparatus for dynamically reconfiguring a processor involves placing the processor in a first configuration having a first number (m) of strands while the coded instructions comprise instructions from a number (m) threads. The instructions in each of the m threads are executed on one of the m strands using execution resources at least some of which are shared among the m strands. While the coded instructions comprise instructions from a number (n) threads, the processor is placed in a second configuration having a second number (n) of strands. The instruction are executed in each of the n strands using execution resources at least some of which are shared among the n strands.
摘要翻译：用于动态地重新配置处理器的方法和装置涉及将处理器置于具有第一数量（m）股线的第一配置中，而编码指令包括数（m）个线程的指令。每个m个线程中的指令在m个线之一上使用执行资源执行，其中至少一些在m个线之间共享。虽然编码的指令包括来自数个（n）个线程的指令，但是处理器被置于具有第二数量（n）个线束的第二配置中。使用执行资源在n个链中的每一个执行指令，其中至少一些在n个链之间共享。

4. 发明授权

US6081873A In-line bank conflict detection and resolution in a multi-ported non-blocking cache 失效
标题翻译：多端口非阻塞缓存中的在线银行冲突检测和解析
公开(公告)号：US6081873A
公开(公告)日：2000-06-27
申请号：US881065
申请日：1997-06-25
申请人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
发明人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0851
摘要： A data cache unit associated with a processor, the data cache unit including a multi-ported non-blocking cache receiving a data access request from a lower level device in the processor. A memory scheduling window includes at least one row of entries, wherein each entry includes an address field holding an address of the access request. A conflict map field within at least some of the entries is coupled to a conflict checking unit. The conflict checking unit responds to the address fields by setting bits in the conflict map fields to indicate intra-row conflicts between entries. A picker coupled to the memory scheduling window responds to the conflict map fields so as to identify groups of non-conflicting entries to launch in parallel at the multi-ported non-blocking cache.
摘要翻译：与处理器相关联的数据高速缓存单元，所述数据高速缓存单元包括从所述处理器中的较低级别的设备接收数据访问请求的多端口非阻塞高速缓存。存储器调度窗口包括至少一行条目，其中每个条目包括保存访问请求的地址的地址字段。至少一些条目内的冲突映射字段被耦合到冲突检查单元。冲突检查单元通过设置冲突映射字段中的位来指示地址字段以指示条目之间的行内冲突。耦合到存储器调度窗口的选择器响应于冲突映射字段，以便识别在多端口非阻塞高速缓存上并行启动的非冲突条目的组。

5. 发明授权

US6006326A Apparatus for restraining over-eager load boosting in an out-of-order machine using a memory disambiguation buffer for determining dependencies 失效
标题翻译：用于使用用于确定依赖性的存储器消歧缓冲器来限制在无序机器中的过度加载增强的装置
公开(公告)号：US6006326A
公开(公告)日：1999-12-21
申请号：US882525
申请日：1997-06-25
申请人： Ramesh Panwar , Ricky C. Hetherington
发明人： Ramesh Panwar , Ricky C. Hetherington
IPC分类号： G06F9/38 , G06F13/00
CPC分类号： G06F9/3834 , G06F9/3838 , G06F9/3861
摘要： A system for restraining over-eager boosting of load instructions past store instructions in an out-of-order processor. The system comprises a memory disambiguation buffer for storing load and store instruction addresses and associated data and an instruction scheduling window in operative association with the memory disambiguation buffer. The instruction scheduling window and the memory disambiguation buffer determine load/store dependencies and effectuate replay of the store and load instructions wherein a dependent load instruction has been executed prior to a store instruction. An instruction cache is provided in operative association with the memory disambiguation buffer, together to associate the dependent load instructions with a store instruction such that the store instruction is subsequently executed prior to the dependent load instructions.
摘要翻译：一种用于在无序处理器中超过存储指令来抑制加载指令的过度增强的系统。该系统包括用于存储负载和存储指令地址和相关数据的存储器消歧缓冲器和与存储器消歧缓冲器可操作地相关联的指令调度窗口。指令调度窗口和存储器消歧缓冲器确定加载/存储相关性并且实现存储和加载指令的重放，其中在存储指令之前已经执行了依赖加载指令。提供与存储器消歧缓冲器可操作地相关联的指令高速缓存器，一起将依赖负载指令与存储指令相关联，使得存储指令随后在依赖加载指令之前执行。

6. 发明授权

US5999727A Method for restraining over-eager load boosting using a dependency color indicator stored in cache with both the load and store instructions 失效
标题翻译：使用存储在高速缓存中的依赖颜色指示符同时加载和存储指令来限制过度加载加载的方法
公开(公告)号：US5999727A
公开(公告)日：1999-12-07
申请号：US882174
申请日：1997-06-25
申请人： Ramesh Panwar , Ricky C. Hetherington
发明人： Ramesh Panwar , Ricky C. Hetherington
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/30112 , G06F9/3834 , G06F9/3838 , G06F9/384
摘要： A system, apparatus and method which functions to restrain over-eager load boosting in an out-of-order processor through the implementation of a special "coloring" mechanism that colors dependent load and store instructions to ensure recognition of a dependency based on the assignment of a common multi-bit "color" scheme. In an exemplary embodiment, two bits of color are assigned to load and store instructions. These color bits are stored in a special array and are read when the load or store is read from the instruction cache ("I$"). The encoding of "00" for a load, for example, may indicate no coloring dependency for the load. Any encoding other than a "00" is utilized to indicate a store-load dependence for a store and load of the same color. The color bits for the load and store instructions are updated when a read-after-write ("RAW") hazard is detected by the memory disambiguation buffer ("MDB") for a store-load pair. The processor dependency tracking logic will enforce a dependency between a store and load of the same color (other than "00") and the instruction scheduling window ("ISW") will not boost the load past the store. Moreover, the instruction scheduling window will schedule the load for fetching data from the memory disambiguation buffer rather than the data cache ("D$").
摘要翻译：一种系统，装置和方法，其功能是通过实施颜色相关的负载和存储指令以确保基于分配的依赖性的识别的特殊的“着色”机制来抑制无序处理器中的过度负载增强的普通多位“彩色”方案。在示例性实施例中，分配两位颜色以加载和存储指令。这些颜色位被存储在一个特殊的数组中，当从指令高速缓存（“I $”）中读取加载或存储时读取它们。例如，对于负载的“00”的编码可以表示对于负载没有着色依赖性。使用除“00”之外的任何编码来指示存储器的存储负载依赖性和相同颜色的负载。当存储负载对的存储器消歧缓冲区（“MDB”）检测到写后读取（“RAW”）危险时，用于加载和存储指令的颜色位被更新。处理器依赖跟踪逻辑将强制存储和相同颜色（“00”之外）的加载之间的依赖关系，并且指令调度窗口（“ISW”）将不会增加经过存储的负载。此外，指令调度窗口将调度从存储器消歧缓冲区而不是数据高速缓存（“D $”）获取数据的负载。

7. 发明授权

US06154812A Method for inhibiting thrashing in a multi-level non-blocking cache system 失效
标题翻译：在多级非阻塞缓存系统中抑制抖动的方法
公开(公告)号：US06154812A
公开(公告)日：2000-11-28
申请号：US881725
申请日：1997-06-25
申请人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
发明人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
IPC分类号： G06F12/08
CPC分类号： G06F12/0897
摘要： A data cache unit associated with a processor, the data cache unit including a first non-blocking cache receiving a data access from a device in the processor. A second non-blocking cache is coupled to the first non-blocking cache to service misses in the first non-blocking cache. A data return path coupled to the second non-blocking cache couples data returning from the second non-blocking cache to both the first non-blocking cache and the device generating the access to the first non-blocking cache.
摘要翻译：与处理器相关联的数据高速缓存单元，所述数据高速缓存单元包括从所述处理器中的设备接收数据访问的第一非阻塞缓存。第二非阻塞高速缓存耦合到第一非阻塞高速缓存以服务第一非阻塞高速缓存中的未命中。耦合到第二非阻塞缓存的数据返回路径将从第二非阻塞高速缓存返回的数据与第一非阻塞高速缓存和产生对第一非阻塞高速缓存的访问的设备耦合。

8. 发明授权

US5978864A Method for thermal overload detection and prevention for an intergrated circuit processor 失效
标题翻译：热过载保护方法，当超过热阈值时，产生不可屏蔽的中断，以降低集成电路的时钟频率
公开(公告)号：US5978864A
公开(公告)日：1999-11-02
申请号：US882610
申请日：1997-06-25
申请人： Ricky C. Hetherington , Ramesh Panwar
发明人： Ricky C. Hetherington , Ramesh Panwar
IPC分类号： G06F1/20 , G06F9/38 , G06F1/08 , G06F13/00
CPC分类号： G06F9/3891 , G06F1/206 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3857 , G06F9/3869 , G06F9/3885 , Y02B60/1275
摘要： A system and method for thermal overload detection and protection for a processor which allows the processor to run at near maximum potential for the vast majority of its execution life. This is effectuated by the provision of circuitry to detect when the processor has exceeded its thermal thresholds and which then causes the processor to automatically reduce the clock rate to a fraction of the nominal clock while execution continues. When the thermal condition has stabilized, the clock may be raised in a stepwise fashion back to the nominal clock rate. Throughout the period of cycling the clock frequency from nominal to minimum and back, the program continues to be executed. Also provided is a queue activity rise time detector and method to control the rate of acceleration of a functional unit from idle to full throttle by a localized stall mechanism at the boundary of each stage in the pipe. This mechanism can detect when an idle queue is suddenly overwhelmed with input such that over a short period of approximately 10-20 machine cycles, the queue activity rate has increased from idle to near stall threshold.
摘要翻译：一种用于处理器的热过载检测和保护的系统和方法，其允许处理器在其绝大多数执行寿命期间以接近最大潜力运行。这通过提供电路来检测何时处理器已经超过其热阈值并且然后使处理器在执行继续时自动将时钟速率降低到标称时钟的一小部分来实现。当热条件稳定时，时钟可以逐步升高回到标称时钟速率。在将时钟频率从标称到最小和反向的整个周期期间，程序继续执行。还提供了一种队列活动上升时间检测器和方法，用于通过在管道中的每个阶段的边界处的局部失速机构来控制功能单元从怠速到全节气门的加速率。这种机制可以检测空闲队列何时突然被输入压倒，使得在大约10-20个机器周期的短时间内，队列活动速率已经从空闲增加到接近失速阈值。

9. 发明授权

US5930819A Method for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cache 失效
标题翻译：在多端口非阻塞缓存中执行串行库冲突检测和解析的方法
公开(公告)号：US5930819A
公开(公告)日：1999-07-27
申请号：US881238
申请日：1997-06-25
申请人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
发明人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0851 , G06F12/0857
摘要： A data cache unit associated with a processor, the data cache unit including a multi-ported non-blocking cache receiving a data access request from a lower level device in the processor. A memory scheduling window includes at least one row of entries, wherein each entry includes an address field holding an address of the access request. A conflict map field within at least some of the entries is coupled to a conflict checking unit. The conflict checking unit responds to the address fields by setting bits in the conflict map fields to indicate intra-row conflicts between entries. A picker coupled to the memory scheduling window responds to the conflict map fields so as to identify groups of non-conflicting entries to launch in parallel at the multi-ported non-blocking cache.
摘要翻译：与处理器相关联的数据高速缓存单元，所述数据高速缓存单元包括从所述处理器中的较低级别的设备接收数据访问请求的多端口非阻塞高速缓存。存储器调度窗口包括至少一行条目，其中每个条目包括保存访问请求的地址的地址字段。至少一些条目内的冲突映射字段被耦合到冲突检查单元。冲突检查单元通过设置冲突映射字段中的位来指示地址字段来指示条目之间的行内冲突。耦合到存储器调度窗口的选择器响应于冲突映射字段，以便识别在多端口非阻塞高速缓存上并行启动的非冲突条目的组。

10. 发明授权

US06240502B1 Apparatus for dynamically reconfiguring a processor 失效
标题翻译：用于动态重新配置处理器的装置
公开(公告)号：US06240502B1
公开(公告)日：2001-05-29
申请号：US08881145
申请日：1997-06-25
申请人： Ramesh Panwar , Ricky C. Hetherington
发明人： Ramesh Panwar , Ricky C. Hetherington
IPC分类号： G06F938
CPC分类号： G06F9/3851 , G06F9/5011 , G06F2209/507
摘要： A method and apparatus for dynamically reconfiguring a processor involves placing the processor in a first configuration having a first number (m) of strands while the coded instructions comprise instructions from a number (m) threads. The instructions in each of the m threads are executed on one of the m strands using execution resources at least some of which are shared among the m strands. While the coded instructions comprise instructions from a number (n) threads, the processor is placed in a second configuration having a second number (n) of strands. The instruction are executed in each of the n strands using execution resources at least some of which are shared among the n strands.
摘要翻译：用于动态地重新配置处理器的方法和装置涉及将处理器置于具有第一数量（m）股线的第一配置中，而编码指令包括数（m）个线程的指令。每个m个线程中的指令在m个线之一上使用执行资源执行，其中至少一些在m个线之间共享。虽然编码的指令包括来自数个（n）个线程的指令，但是处理器被置于具有第二数量（n）个线束的第二配置中。使用执行资源在n个链中的每一个执行指令，其中至少一些在n个链之间共享。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式