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1. 发明申请

US20060085602A1 Method and apparatus for initiating CPU data prefetches by an external agent 失效
标题翻译：用于由外部代理启动CPU数据预取的方法和装置
公开(公告)号：US20060085602A1
公开(公告)日：2006-04-20
申请号：US10966231
申请日：2004-10-15
申请人： Ramakrishna Huggahalli , Brannon Batson , Raymond Tetrick , Robert Blankenship
发明人： Ramakrishna Huggahalli , Brannon Batson , Raymond Tetrick , Robert Blankenship
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/345 , G06F12/0862 , G06F2212/6028
摘要： An arrangement is provided for an external agent to initiate data prefetches from a system memory to a cache associated with a target processor, which needs the data to execute a program, in a computing system. When the external agent has data, it may create and issue a prefetch directive. The prefetch directive may be sent along with system interconnection transactions or sent as a separate transaction to devices including the target processor in the system. When receiving and recognizing the prefetch directive, a hardware prefetcher associated with the target processor may issue a request to the system memory to prefetch data to the cache. The target processor can access data in the cache more efficiently than it accesses data in the system memory. Some pre-processing may also be associated with the data prefetch.
摘要翻译：提供了一种用于外部代理在计算系统中启动从系统存储器到与目标处理器相关联的高速缓存（其需要数据执行程序）的安排。外部代理具有数据时，可能会创建并发出预取指令。预取指令可以与系统互连事务一起发送，或作为单独事务发送到包括系统中的目标处理器的设备。当接收和识别预取指令时，与目标处理器相关联的硬件预取器可以向系统存储器发出请求以将数据预取到高速缓存。目标处理器可以比访问系统内存中的数据更有效地访问高速缓存中的数据。一些预处理也可能与数据预取相关联。

2. 发明授权

US07502877B2 Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor system 有权
标题翻译：动态设置路由信息，将输入输出数据直接传输到多处理器系统中的处理器高速缓存中
公开(公告)号：US07502877B2
公开(公告)日：2009-03-10
申请号：US11749286
申请日：2007-05-16
申请人： Ram Huggahalli , Raymond Tetrick
发明人： Ram Huggahalli , Raymond Tetrick
IPC分类号： G06F3/00 , G06F13/28 , G06F13/00
CPC分类号： G06F13/4027 , G06F12/0806 , G06F12/0835
摘要： According to some embodiments, IO traffic is transferred directly into a target processor cache in accordance with routing information.
摘要翻译：根据一些实施例，根据路由信息将IO流量直接传送到目标处理器高速缓存。

3. 发明申请

US20060294277A1 Message signaled interrupt redirection 审中-公开
标题翻译：消息指示中断重定向
公开(公告)号：US20060294277A1
公开(公告)日：2006-12-28
申请号：US11165732
申请日：2005-06-24
申请人： Raymond Tetrick
发明人： Raymond Tetrick
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A method, device, and system are disclosed. In one embodiment, the method comprises receiving a message signaled interrupt, parsing an interrupt vector from the message signaled interrupt, locating an interrupt entry associated with the interrupt vector in a table of interrupt entries, and sending information associated with the interrupt entry to a processor.
摘要翻译：公开了一种方法，装置和系统。在一个实施例中，该方法包括接收消息信号中断，从消息信号中断解析中断向量，将与中断向量相关联的中断条目定位在中断条目表中，以及将与中断条目相关联的信息发送到处理器。

4. 发明申请

US20070214307A1 DYNAMICALLY SETTING ROUTING INFORMATION TO TRANSFER INPUT OUTPUT DATA DIRECTLY INTO PROCESSOR CACHES IN A MULTI PROCESSOR SYSTEM 有权
标题翻译：动态设置路由信息，将输入输出数据直接传输到多处理器系统中的处理器缓存
公开(公告)号：US20070214307A1
公开(公告)日：2007-09-13
申请号：US11749286
申请日：2007-05-16
申请人： Ram Huggahalli , Raymond Tetrick
发明人： Ram Huggahalli , Raymond Tetrick
IPC分类号： G06F13/00
CPC分类号： G06F13/4027 , G06F12/0806 , G06F12/0835
摘要： According to some embodiments, IO traffic is transferred directly into a target processor cache in accordance with routing information.
摘要翻译：根据一些实施例，根据路由信息将IO流量直接传送到目标处理器高速缓存。

5. 发明申请

US20070002760A1 Virtualization of pin functionality in a point-to-point interface 有权
标题翻译：在点对点接口中实现引脚功能的虚拟化
公开(公告)号：US20070002760A1
公开(公告)日：2007-01-04
申请号：US11173643
申请日：2005-06-30
申请人： Keshavan Tiruvallur , David Poisner , Herbert Hum , Frank Binns , David Hill , Robert Greiner , Raymond Tetrick
发明人： Keshavan Tiruvallur , David Poisner , Herbert Hum , Frank Binns , David Hill , Robert Greiner , Raymond Tetrick
IPC分类号： H04J1/16
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Architectures and techniques that allow legacy pin functionality to be replaced with a “virtual wire” that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.
摘要翻译：允许传统引脚功能被替换为“虚拟线”的架构和技术，“虚拟线”可以传达否则将由有线接口传送的信息。可以在系统控制器和包括虚拟线路值和虚拟换线指示器的处理器之间传递消息。虚拟线值可以包括对应于已经从物理接口消除的一个或多个引脚的信号，并且虚拟线更改值可以包括虚拟线值是否已经改变的指示。虚拟线路值和虚拟线路变化指示器的组合可以允许多个物理引脚被消息值替换。

6. 发明申请

US20050210229A1 Method and system for configuration of processor integrated devices in multi-processor systems 审中-公开
标题翻译：在多处理器系统中配置处理器集成设备的方法和系统
公开(公告)号：US20050210229A1
公开(公告)日：2005-09-22
申请号：US10806787
申请日：2004-03-22
申请人： Prashant Sethi , Kenneth Creta , Raymond Tetrick
发明人： Prashant Sethi , Kenneth Creta , Raymond Tetrick
IPC分类号： G06F15/16 , G06F9/445 , G06F13/40 , G06F9/00
CPC分类号： G06F13/4027
摘要： The ability to configure an integrated device with a decoder in a processor or network component according to PCI or PCI Express interconnects.
摘要翻译：根据PCI或PCI Express互连，能够在处理器或网络组件中配置具有解码器的集成设备。

7. 发明授权

US07231470B2 Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor system 有权
标题翻译：动态设置路由信息，将输入输出数据直接传输到多处理器系统中的处理器高速缓存中
公开(公告)号：US07231470B2
公开(公告)日：2007-06-12
申请号：US10736765
申请日：2003-12-16
申请人： Ram Huggahalli , Raymond Tetrick
发明人： Ram Huggahalli , Raymond Tetrick
IPC分类号： G06F3/00 , G06F13/28 , G06F13/00
CPC分类号： G06F13/4027 , G06F12/0806 , G06F12/0835
摘要： According to some embodiments, IO traffic is transferred directly into a target processor cache in accordance with routing information. For example, it may be determined at a requesting agent processor that IO traffic is to be received at the target processor cache, wherein the target processor is different than the requesting agent processor. Moreover, routing information associated with the IO traffic may be received from the requesting agent processor. It may then be arranged for the IO traffic to be transferred directly into the target processor cache in accordance with the routine information.
摘要翻译：根据一些实施例，根据路由信息将IO流量直接传送到目标处理器高速缓存。例如，可以在请求代理处理器处确定在目标处理器高速缓存处接收IO业务，其中目标处理器不同于请求代理处理器。此外，可以从请求代理处理器接收与IO流量相关联的路由信息。然后可以根据例程信息将IO通信量直接传送到目标处理器高速缓存。

8. 发明申请

US20050223383A1 Methods and apparatus for reserving an execution thread 审中-公开
标题翻译：用于保留执行线程的方法和装置
公开(公告)号：US20050223383A1
公开(公告)日：2005-10-06
申请号：US10813794
申请日：2004-03-31
申请人： Raymond Tetrick
发明人： Raymond Tetrick
IPC分类号： G06F9/445 , G06F9/46 , G06F9/50
CPC分类号： G06F9/5011 , G06F9/4411
摘要： Methods and apparatuses for reserving an execution thread are disclosed. A selected processing unit is described as a peripheral device in a device description. Peripheral devices are prevented from using the selected processing unit. A processor description includes one or more available processing units, and omits the selected processing unit. The processor description is provided to an operating system. The device description of the selected processing unit may be read and recognized as a device description of a peripheral device. A device driver may be retrieved for the processing units based on the device description of the processing unit, and resources may be allocated to the processing unit based on a request from the driver.
摘要翻译：公开了用于保留执行线程的方法和装置。在设备描述中将所选择的处理单元描述为外围设备。防止外围设备使用所选择的处理单元。处理器描述包括一个或多个可用处理单元，并省略所选择的处理单元。处理器描述被提供给操作系统。可以将所选择的处理单元的设备描述读取并识别为外围设备的设备描述。可以基于处理单元的设备描述为处理单元检索设备驱动程序，并且可以基于来自驾驶员的请求将资源分配给处理单元。

9. 发明申请

US20050132102A1 Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor system 有权
标题翻译：动态设置路由信息，将输入输出数据直接传输到多处理器系统中的处理器高速缓存中
公开(公告)号：US20050132102A1
公开(公告)日：2005-06-16
申请号：US10736765
申请日：2003-12-16
申请人： Ram Huggahalli , Raymond Tetrick
发明人： Ram Huggahalli , Raymond Tetrick
IPC分类号： G06F12/08 , G06F13/00 , G06F13/40
CPC分类号： G06F13/4027 , G06F12/0806 , G06F12/0835
摘要： According to some embodiments, IO traffic is transferred directly into a target processor cache in accordance with routing information.
摘要翻译：根据一些实施例，根据路由信息将IO流量直接传送到目标处理器高速缓存。

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