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1. 发明申请

US20050260801A1 High performance FET with elevated source/drain region 失效
标题翻译：具有升高的源极/漏极区域的高性能FET
公开(公告)号：US20050260801A1
公开(公告)日：2005-11-24
申请号：US10996866
申请日：2004-11-24
申请人： Rama Divakaruni , Louis Hsu , Rajiv Joshi , Carl Radens
发明人： Rama Divakaruni , Louis Hsu , Rajiv Joshi , Carl Radens
IPC分类号： H01L21/336 , H01L29/45 , H01L29/76 , H01L29/786
CPC分类号： H01L29/66553 , H01L29/458 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66772 , H01L29/7842 , H01L29/78618 , H01L29/78684
摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.
摘要翻译：包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 FET包括在绝缘体层上的每个端部（例如，在绝缘体上的超薄绝缘体（SOI））芯片上的源极/漏极（RSD）区域上升的薄沟道。在FET的每个端部，即在RSD区域的末端处的隔离沟槽隔离并限定FET岛。每个RSD区域的绝缘侧壁将RSD区域之间的FET栅极夹在中间。栅极电介质可以是高K电介质。 RSD区域上和可选地在栅极上的杀菌剂降低了器件电阻。

2. 发明授权

US06762447B1 Field-shield-trench isolation for gigabit DRAMs 有权
标题翻译：用于千兆位DRAM的场屏蔽沟槽隔离
公开(公告)号：US06762447B1
公开(公告)日：2004-07-13
申请号：US09245269
申请日：1999-02-05
申请人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
发明人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L21/763 , H01L21/765 , H01L27/10829 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.
摘要翻译：形成在半导体主体中的动态随机存取存储器（DRAM）具有通过垂直电隔离沟槽彼此隔离并且与支持电路隔离的各对存储单元。隔离沟槽具有侧壁和上部和下部，并且包围包含存储单元的半导体主体的区域。这使得存储器单元对彼此和从包含在半导体本体内但不位于包围区域内的支撑电路电隔离。隔离沟槽的下部填充有导电材料，该导电材料具有其侧壁部分，其侧壁部分通过第一电绝缘体至少部分地与沟槽的下部的侧壁分离，并且其具有位于与半导体本体电接触。隔离沟槽的上部填充有第二电绝缘体。

3. 发明授权

US06288422B1 Structure and process for fabricating a 6F2 DRAM cell having vertical MOSFET and large trench capacitance 失效
标题翻译：用于制造具有垂直MOSFET和大沟槽电容的6F2 DRAM单元的结构和工艺
公开(公告)号：US06288422B1
公开(公告)日：2001-09-11
申请号：US09540276
申请日：2000-03-31
申请人： Jack A. Mandelman , Rama Divakaruni , Carl Radens
发明人： Jack A. Mandelman , Rama Divakaruni , Carl Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , H01L27/10891 , H01L29/945
摘要： A 6F2 memory cell structure comprising a plurality of capacitors each located in a separate trench in a substrate; a pluralaity of transfer transistors each having a vertical gate dielectric, a gate conductor, and a bitline diffusion, each transistor being located above and electrically connected to a respective trench capacitor; a plurality of troughs in a striped pattern about said transistor, said troughs being spaced apart by a substantially uniform spacing, said plurality of striped troughs comprising a first group of troughs consisting of every other one of said troughs being filled with a dielectric material, and a second group of troughs being the remaining troughs of said plurality, said second group of troughs containing dielectric material, damascened wordlines and damascene wordline contacts; a respective wordline electrical contact connected to each respective gate conductor; and a bitline contacted to each bitline diffusion, wherein said bitline diffusions have a width defined by said spacing of said striped troughs and each wordline electrical contact is self-aligned to an edge of a trough of said second group of troughs.
摘要翻译： 6F2存储器单元结构，包括多个电容器，每个电容器位于衬底中的单独的沟槽中; 每个具有垂直栅极电介质，栅极导体和位线扩散的转移晶体管的多个，每个晶体管位于相应的沟槽电容器的上方并电连接到相应的沟槽电容器; 围绕所述晶体管的条纹图案的多个槽，所述槽以基本上均匀的间隔间隔开，所述多个条纹槽包括由每一个所述槽中的每一个填充有电介质材料构成的第一组槽，以及第二组槽是所述多个的剩余槽，所述第二组槽包含电介质材料，大阴影字线和大马士革字线触点; 连接到每个相应的栅极导体的相应字线电触头; 并且与每个位线扩散接触的位线，其中所述位线扩散具有由所述条纹槽的所述间隔限定的宽度，并且每个字线电触点与所述第二组槽的槽的边缘自对准。

4. 发明授权

US07473979B2 Semiconductor integrated circuit devices having high-Q wafer back-side capacitors 有权
标题翻译：具有高Q晶片背面电容器的半导体集成电路器件
公开(公告)号：US07473979B2
公开(公告)日：2009-01-06
申请号：US11443394
申请日：2006-05-30
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/92
CPC分类号： H01L21/84 , H01L21/76898 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

5. 发明申请

US20070164357A1 Structure and method for MOSFET gate electrode landing pad 有权
标题翻译： MOSFET栅极电极着陆焊盘的结构和方法
公开(公告)号：US20070164357A1
公开(公告)日：2007-07-19
申请号：US11333068
申请日：2006-01-17
申请人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens , Keith Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens , Keith Wong , Chih-Chao Yang
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译：晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

6. 发明申请

US20060043435A1 Nano-scaled gate structure with self-interconnect capabilities 失效
公开(公告)号：US20060043435A1
公开(公告)日：2006-03-02
申请号：US10930989
申请日：2004-08-31
申请人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens , Keith Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens , Keith Wong , Chih-Chao Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/28114 , H01L21/76895 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/0629 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545
摘要： Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device comprises two gate conductors with enlarged upper portions which merge to create electrically interconnected gate conductors. Methods for forming the above semiconductor devices are also described and claimed.

7. 发明申请

US20050180521A1 REDUNDANCY STRUCTURE AND METHOD FOR HIGH-SPEED SERIAL LINK 失效
标题翻译：用于高速串行链路的冗余结构和方法
公开(公告)号：US20050180521A1
公开(公告)日：2005-08-18
申请号：US10708240
申请日：2004-02-18
申请人： Louis Hsu , Carl Radens , Li-Kong Wang
发明人： Louis Hsu , Carl Radens , Li-Kong Wang
IPC分类号： H04L1/22 , H04L25/02 , H04L25/08 , H04L27/04
CPC分类号： H04L1/22 , H04L25/029 , H04L25/08
摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.
摘要翻译：提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射机连接到该输出信号线来代替故障数据发射机。在一个优选形式中，连接元件包括保险丝和反熔丝。在另一种形式中，连接元件包括微机电（MEM）开关。连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。

8. 发明授权

US07531407B2 Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same 失效
标题翻译：具有高Q晶片背面电感器的半导体集成电路器件及其制造方法
公开(公告)号：US07531407B2
公开(公告)日：2009-05-12
申请号：US11488242
申请日：2006-07-18
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/8234
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面上的高Q片上电感器，并且使用晶片间互连连接到芯片前端的集成电路。例如，具有背面集成电感器的半导体器件包括半导体衬底，其具有插入在衬底的前侧和后侧之间的前侧，后侧和掩埋绝缘层。在半导体衬底的前侧形成集成电路，在半导体衬底的背面形成集成电感器。通过埋层绝缘层形成互连结构，将集成电感器连接到集成电路。半导体衬底可以是SOI（绝缘体上硅）结构。

9. 发明申请

US20080092367A1 MICRO-CAVITY MEMS DEVICE AND METHOD OF FABRICATING SAME 失效
标题翻译：微孔MEMS器件及其制造方法
公开(公告)号：US20080092367A1
公开(公告)日：2008-04-24
申请号：US11968896
申请日：2008-01-03
申请人： Louis Hsu , Lawrence Clevenger , Timothy Dalton , Carl Radens , Keith Wong , Chih-Chao Yang
发明人： Louis Hsu , Lawrence Clevenger , Timothy Dalton , Carl Radens , Keith Wong , Chih-Chao Yang
IPC分类号： H01H11/00 , H01F41/04
CPC分类号： H01H50/005 , H01H2050/007 , Y10T29/4902 , Y10T29/49105 , Y10T29/49147
摘要： A method of fabricating a MEMS switch having a free moving inductive element within in micro-cavity guided by at least one inductive coil. The switch consists of an upper inductive coil at one end of a micro-cavity; optionally, a lower inductive coil; and a free-moving inductive element preferably made of magnetic material. The coils are provided with an inner permalloy core. Switching is achieved by passing a current through the upper coil, inducing a magnetic field unto the inductive element. The magnetic field attracts the free-moving inductive element upwards, shorting two open conductive wires, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the conductive wires open. When the chip is not mounted with the correct orientation, the lower coil pulls the free-moving inductive element back at its original position.
摘要翻译：一种制造具有由至少一个感应线圈引导的微腔内的自由运动的感应元件的MEMS开关的方法。开关由微腔一端的上感应线圈组成; 可选地，下感应线圈; 以及优选由磁性材料制成的自由移动的电感元件。线圈设有内坡道合金芯。通过使电流通过上部线圈，从而产生电感元件的磁场来实现切换。磁场向上吸引自由移动的感应元件，短路两根开放的导线，闭合开关。当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且导线打开。当芯片没有以正确的方向安装时，下线圈将自由移动的感应元件拉回其原始位置。

10. 发明申请

US20080020488A1 Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same 失效
标题翻译：具有高Q晶片背面电感器的半导体集成电路器件及其制造方法
公开(公告)号：US20080020488A1
公开(公告)日：2008-01-24
申请号：US11488242
申请日：2006-07-18
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/00
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面上的高Q片上电感器，并且使用晶片间互连连接到芯片前端的集成电路。例如，具有背面集成电感器的半导体器件包括半导体衬底，其具有插入在衬底的前侧和后侧之间的前侧，后侧和掩埋绝缘层。在半导体衬底的前侧形成集成电路，在半导体衬底的背面形成集成电感器。通过埋层绝缘层形成互连结构，将集成电感器连接到集成电路。半导体衬底可以是SOI（绝缘体上硅）结构。

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