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1. 发明申请

US20050184359A1 STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR 有权
标题翻译：带有收集器的自对准双极晶体管的结构和方法
公开(公告)号：US20050184359A1
公开(公告)日：2005-08-25
申请号：US10708340
申请日：2004-02-25
申请人： Hiroyuki Akatsu , Rama Divakaruni , Gregory Freeman , David Greenberg , Marwan Khater , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Gregory Freeman , David Greenberg , Marwan Khater , William Tonti
IPC分类号： H01L21/331 , H01L27/082 , H01L29/08 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7378
摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.
摘要翻译：提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积下表面。双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。

2. 发明申请

US20050199907A1 STRUCTURE AND METHOD OF FORMING A BIPOLAR TRANSISTOR HAVING A VOID BETWEEN EMITTER AND EXTRINSIC BASE 失效
标题翻译：形成具有发射极和极端基底之间的空穴的双极晶体管的结构和方法
公开(公告)号：US20050199907A1
公开(公告)日：2005-09-15
申请号：US10708563
申请日：2004-03-11
申请人： Rama Divakaruni , Gregory Freeman , Marwan Khater , William Tonti
发明人： Rama Divakaruni , Gregory Freeman , Marwan Khater , William Tonti
IPC分类号： H01L21/331 , H01L27/06 , H01L27/082 , H01L29/06 , H01L29/737 , H01L31/072
CPC分类号： H01L29/66242 , H01L27/0623 , H01L29/0649 , H01L29/7378
摘要： Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap including at least one of an air gap and a vacuum void.
摘要翻译：提供了用于制造双极晶体管的结构和方法，双极晶体管包括集电极，覆盖集电极的本征基极，覆盖本征基极的发射极以及与发射极间隔开的非本征基极，该间隙至少包括一个气隙和一个真空空隙。

3. 发明授权

US06940149B1 Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base 失效
标题翻译：形成在发射极和非本征基底之间具有空隙的双极晶体管的结构和方法
公开(公告)号：US06940149B1
公开(公告)日：2005-09-06
申请号：US10708563
申请日：2004-03-11
申请人： Rama Divakaruni , Gregory Freeman , Marwan Khater , William Tonti
发明人： Rama Divakaruni , Gregory Freeman , Marwan Khater , William Tonti
IPC分类号： H01L21/331 , H01L27/06 , H01L27/082 , H01L29/06 , H01L29/737 , H01L31/072
CPC分类号： H01L29/66242 , H01L27/0623 , H01L29/0649 , H01L29/7378
摘要： Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap including at least one of an air gap and a vacuum void.
摘要翻译：提供了用于制造双极晶体管的结构和方法，双极晶体管包括集电极，覆盖集电极的本征基极，覆盖本征基极的发射极以及与发射极间隔开的非本征基极，该间隙至少包括一个气隙和一个真空空隙。

4. 发明授权

US07190046B2 Bipolar transistor having reduced collector-base capacitance 失效
标题翻译：双极晶体管具有降低的集电极 - 基极电容
公开(公告)号：US07190046B2
公开(公告)日：2007-03-13
申请号：US10708860
申请日：2004-03-29
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
IPC分类号： H01L27/082 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.
摘要翻译：提供了用于形成双极晶体管的结构和方法。如所公开的，提供覆盖在集电极层上的本征基层。低电容区域横向设置在集电极层附近。低电容区域包括设置在本征基层下面的底切中的电介质区域和空穴中的至少一个。发射极层覆盖本征基极层，凸起的非本征基极层覆盖本征基极层。

5. 发明申请

US20050212087A1 STRUCTURE AND METHOD OF MAKING A BIPOLAR TRANSISTOR HAVING REDUCED COLLECTOR-BASED CAPACITANCE 失效
标题翻译：具有减少集电极电容的双极晶体管的结构和方法
公开(公告)号：US20050212087A1
公开(公告)日：2005-09-29
申请号：US10708860
申请日：2004-03-29
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
IPC分类号： H01L21/331 , H01L27/102 , H01L29/06 , H01L29/08
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.
摘要翻译：提供了用于形成双极晶体管的结构和方法。如所公开的，提供覆盖在集电极层上的本征基层。低电容区域横向设置在集电极层附近。低电容区域包括设置在本征基层下面的底切中的电介质区域和空穴中的至少一个。发射极层覆盖本征基极层，凸起的非本征基极层覆盖本征基极层。

6. 发明申请

US20070096259A1 Fabrication of bipolar transistor having reduced collector-base capacitance 失效
标题翻译：具有减小的集电极 - 基极电容的双极晶体管的制造
公开(公告)号：US20070096259A1
公开(公告)日：2007-05-03
申请号：US11633380
申请日：2006-12-04
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
IPC分类号： H01L27/082
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： A method is provided for fabricating a bipolar transistor in which a collector layer is formed which includes an active portion having a relatively high dopant concentration and a second portion which has a lower dopant concentration. An epitaxial intrinsic base layer is formed to overlie the collector layer in conductive communication with the active portion of the collector layer. A low-capacitance region is formed laterally adjacent to the second portion of the collector layer, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer. An emitter layer is formed to overlie the intrinsic base layer.
摘要翻译：提供一种用于制造双极晶体管的方法，其中形成集电极层，其包括具有较高掺杂剂浓度的有源部分和具有较低掺杂剂浓度的第二部分。外延本征基极层形成为覆盖集电极层，与集电极层的有源部分导电连通。低电容区域形成为与集电极层的第二部分横向相邻，低电容区域包括设置在直接位于本征基极层下方的底切处的电介质区域。形成发射极层以覆盖本征基极层。

7. 发明授权

US07462547B2 Method of fabricating a bipolar transistor having reduced collector-base capacitance 失效
标题翻译：制造具有减小的集电极 - 基极电容的双极晶体管的方法
公开(公告)号：US07462547B2
公开(公告)日：2008-12-09
申请号：US11633380
申请日：2006-12-04
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
IPC分类号： H01L21/331 , H01L27/082
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.
摘要翻译：提供了一种用于制造双极晶体管的方法，该双极晶体管包括将外延层生长到具有低掺杂剂浓度的衬底区域和限定有源区域层的边缘的沟槽隔离区域，通过掩模注入外延层的一部分以限定具有相对较高掺杂剂浓度的集电极区域，所述集电极区域横向邻接所述外延层的具有低掺杂浓度的第二区域; 形成覆盖所述集电极区域和所述第二区域的本征基极层，所述本征基极层包括与所述集电极区域导通连通的外延区域; 形成由所述第二区域与所述集电极区域横向分离的低电容区域，所述低电容区域包括设置在所述本征基极层下方的底切处的电介质区域; 并形成覆盖本征基层的发射极层。

8. 发明授权

US07163864B1 Method of fabricating semiconductor side wall fin 有权
标题翻译：制造半导体侧壁翅片的方法
公开(公告)号：US07163864B1
公开(公告)日：2007-01-16
申请号：US09691353
申请日：2000-10-18
申请人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/78654 , H01L29/78687
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.
摘要翻译：通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。

9. 发明授权

US07030481B2 High density chip carrier with integrated passive devices 有权
标题翻译：具有集成无源器件的高密度芯片载体
公开(公告)号：US07030481B2
公开(公告)日：2006-04-18
申请号：US10314589
申请日：2002-12-09
申请人： Michael Patrick Chudzik , Robert H. Dennard , Rama Divakaruni , Bruce Kenneth Furman , Rajarao Jammy , Chandrasekhar Narayan , Sampath Purushothaman , Joseph F. Shepard, Jr. , Anna Wanda Topol
发明人： Michael Patrick Chudzik , Robert H. Dennard , Rama Divakaruni , Bruce Kenneth Furman , Rajarao Jammy , Chandrasekhar Narayan , Sampath Purushothaman , Joseph F. Shepard, Jr. , Anna Wanda Topol
IPC分类号： H01L23/053
CPC分类号： H05K1/162 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L23/50 , H01L2224/16225 , H01L2924/01019 , H01L2924/01055 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311 , H01L2924/157 , H01L2924/30105 , H05K1/167 , H05K3/4602 , H05K2201/09809
摘要： A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.
摘要翻译：提供了一种用于半导体部件的载体，其具有集成在其基板中的无源部件。无源组件包括去耦组件，例如电容器和电阻器。一组连接被集成以提供与受支持的部件的紧密的电气接近。

10. 发明授权

US06998666B2 Nitrided STI liner oxide for reduced corner device impact on vertical device performance 有权
标题翻译：氮化氮化物衬垫氧化物，用于减少拐角装置对垂直装置性能的影响
公开(公告)号：US06998666B2
公开(公告)日：2006-02-14
申请号：US10707754
申请日：2004-01-09
申请人： Jochen Beintner , Rama Divakaruni , Rajarao Jammy
发明人： Jochen Beintner , Rama Divakaruni , Rajarao Jammy
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10894
摘要： A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.
摘要翻译：一种制造集成电路器件的方法包括蚀刻衬底中的沟槽并形成具有位于下端的存储电容器的动态随机存取存储器（DRAM）单元和覆盖的垂直金属氧化物半导体场效应晶体管（MOSFET），其包括栅极导体和掺硼通道。该方法包括在DRAM单元附近形成沟槽和在DRAM单元的任一侧上与栅极导体相邻的硅 - 氮氧化物隔离衬垫。然后在DRAM单元的两侧的沟槽中形成隔离区。此后，包括与栅极导体相邻的含硼沟道区域的DRAM单元通过热处理受到升高的温度，例如，在邻近隔离区域的衬底上形成支撑器件。与基本上不含氮氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中的硼的偏析。

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