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1. 发明授权

US09113162B2 Dynamic packet size control for MPEG-4 data partition mode 有权
标题翻译：用于MPEG-4数据分区模式的动态分组大小控制
公开(公告)号：US09113162B2
公开(公告)日：2015-08-18
申请号：US12005910
申请日：2007-12-27
申请人： Ram Prabhakar , Harikrishna M. Reddy , Lefan Zhong , Wei Sun , Leonardo Vainsencher , Visalakshi Vaduganathan
发明人： Ram Prabhakar , Harikrishna M. Reddy , Lefan Zhong , Wei Sun , Leonardo Vainsencher , Visalakshi Vaduganathan
IPC分类号： H04N7/12 , H04N19/103 , H04N19/159 , H04N19/176 , H04N19/129 , H04N19/61 , H04N19/593 , H04N19/136 , H04N19/152 , H04N19/48 , H04N19/42 , H04N19/89
CPC分类号： H04N19/103 , H04N19/129 , H04N19/136 , H04N19/152 , H04N19/159 , H04N19/176 , H04N19/42 , H04N19/48 , H04N19/593 , H04N19/61 , H04N19/89
摘要： A dynamic AC prediction technique is implemented in a data partition mode which automatically disables AC prediction for encoding the current macroblock in the next packet when packet overflow occurs. Otherwise, when there is no overflow, AC prediction remains enabled to maintain compression efficiency. More particularly, in the preferred embodiment, a determination is first made whether a macroblock causes a packet overflow if it is encoded in the current packet. If so, a new packet is initiated into which the macroblock is encoded without AC prediction as the first macroblock. Otherwise, the macroblock with AC prediction remains in the current packet and a new macroblock is encoded.
摘要翻译：动态AC预测技术在数据分区模式下实现，当分组溢出发生时，数据分割模式自动禁用AC预测以对下一个分组中的当前宏块进行编码。否则，当没有溢出时，AC预测仍然能够保持压缩效率。更具体地，在优选实施例中，首先确定宏块如果在当前分组中被编码则导致分组溢出。如果是，则发起新的分组，其中宏块被编码而没有AC预测作为第一宏块。否则，具有AC预测的宏块保留在当前分组中，并且对新的宏块进行编码。

2. 发明申请

US20080225957A1 Dynamic packet size control for MPEG-4 data partition mode 审中-公开
公开(公告)号：US20080225957A1
公开(公告)日：2008-09-18
申请号：US12005910
申请日：2007-12-27
申请人： Ram Prabhakar , Harikrishna M. Reddy , Lefan Zhong , Wei Sun , Leonardo Vainsencher , Visalakshi Vaduganathan
发明人： Ram Prabhakar , Harikrishna M. Reddy , Lefan Zhong , Wei Sun , Leonardo Vainsencher , Visalakshi Vaduganathan
IPC分类号： H04N7/26
CPC分类号： H04N19/103 , H04N19/129 , H04N19/136 , H04N19/152 , H04N19/159 , H04N19/176 , H04N19/42 , H04N19/48 , H04N19/593 , H04N19/61 , H04N19/89
摘要： A dynamic AC prediction technique is implemented in a data partition mode which automatically disables AC prediction for encoding the current macroblock in the next packet when packet overflow occurs. Otherwise, when there is no overflow, AC prediction remains enabled to maintain compression efficiency. More particularly, in the preferred embodiment, a determination is first made whether a macroblock causes a packet overflow if it is encoded in the current packet. If so, a new packet is initiated into which the macroblock is encoded without AC prediction as the first macroblock. Otherwise, the macroblock with AC prediction remains in the current packet and a new macroblock is encoded.

3. 发明申请

US20080170614A1 Dynamic packet size control for MPEG-4 data partition mode 审中-公开
标题翻译：用于MPEG-4数据分区模式的动态分组大小控制
公开(公告)号：US20080170614A1
公开(公告)日：2008-07-17
申请号：US12005861
申请日：2007-12-27
申请人： Ram Prabhakar , Harikrishna M. Reddy , Lefan Zhong , Wei Sun , Leonardo Vainsencher , Visalakshi Vaduganathan
发明人： Ram Prabhakar , Harikrishna M. Reddy , Lefan Zhong , Wei Sun , Leonardo Vainsencher , Visalakshi Vaduganathan
IPC分类号： H04N7/12 , H04N11/04 , H04B1/66 , H04N11/02
CPC分类号： H04N19/103 , H04N19/129 , H04N19/136 , H04N19/152 , H04N19/159 , H04N19/176 , H04N19/42 , H04N19/48 , H04N19/593 , H04N19/61 , H04N19/89
摘要： A dynamic AC prediction technique is implemented in a data partition mode which automatically disables AC prediction for encoding the current macroblock in the next packet when packet overflow occurs. Otherwise, when there is no overflow, AC prediction remains enabled to maintain compression efficiency. More particularly, in the preferred embodiment, a determination is first made whether a macroblock causes a packet overflow if it is encoded in the current packet. If so, a new packet is initiated into which the macroblock is encoded without AC prediction as the first macroblock. Otherwise, the macroblock with AC prediction remains in the current packet and a new macroblock is encoded.
摘要翻译：动态AC预测技术在数据分区模式下实现，当分组溢出发生时，数据分割模式自动禁用AC预测以对下一个分组中的当前宏块进行编码。否则，当没有溢出时，AC预测仍然能够保持压缩效率。更具体地，在优选实施例中，首先确定宏块如果在当前分组中被编码则导致分组溢出。如果是，则发起新的分组，其中宏块被编码而没有AC预测作为第一宏块。否则，具有AC预测的宏块保留在当前分组中，并且对新的宏块进行编码。

4. 发明授权

US07792891B2 Forward discrete cosine transform engine 有权
标题翻译：前向离散余弦变换引擎
公开(公告)号：US07792891B2
公开(公告)日：2010-09-07
申请号：US10316394
申请日：2002-12-11
申请人： Leonardo Vainsencher , Cahide Kiris
发明人： Leonardo Vainsencher , Cahide Kiris
IPC分类号： G06F17/14
CPC分类号： G06F17/147 , G06T9/007
摘要： Systems and methods are disclosed to perform fast discrete cosine transform (DCT) by computing the DCT in five stages using three coefficients, and scaling the outputs using a plurality of scaling coefficients.
摘要翻译：公开了通过使用三个系数在五个阶段中计算DCT并使用多个缩放系数对输出进行缩放来执行快速离散余弦变换（DCT）的系统和方法。

5. 发明授权

US07659778B2 Apparatus and method for class D amplifier with sampling rate conversion 有权
标题翻译：具有采样率转换的D类放大器的装置和方法
公开(公告)号：US07659778B2
公开(公告)日：2010-02-09
申请号：US12186232
申请日：2008-08-05
申请人： Leonardo Vainsencher
发明人： Leonardo Vainsencher
IPC分类号： H03F3/38
CPC分类号： H03F3/217
摘要： A class D amplifier is provided. The class D amplifier includes an interpolator, a sampling rate converter, a pulse width modulator, a sigma-delta modulator, and a pulse width modulation (PWM) pulse generator (PPG). The sampling rate converter interpolates the output of the interpolator such that the sampling rate converter up-samples the interpolator output by a factor that is greater than one and less than two. The pulse width modulator outputs a multi-bit digital signal. The sigma-delta modulator performs sigma-delta modulation on the pulse width modulator output, the order of the sigma-delta modulation is programmable, and the output of the sigma-delta modulator is a multi-bit, digital signal. At least one of the orders to which the sigma-delta modulator can be programmed is greater than two. The PPG provides a pulse signal such that the width of each pulse is based on the value of the sigma-delta modulator output.
摘要翻译：提供D类放大器。 D类放大器包括内插器，采样率转换器，脉冲宽度调制器，Σ-Δ调制器和脉冲宽度调制（PWM）脉冲发生器（PPG）。采样率转换器内插内插器的输出，使得采样率转换器将内插器输出上采样大于1且小于2的因子。脉冲宽度调制器输出多位数字信号。 Σ-Δ调制器在脉冲宽度调制器输出上执行Σ-Δ调制，Σ-Δ调制的顺序是可编程的，Σ-Δ调制器的输出是多位数字信号。 Σ-Δ调制器可编程的顺序中的至少一个大于2。 PPG提供脉冲信号，使得每个脉冲的宽度基于Σ-Δ调制器输出的值。

6. 发明申请

US20140082241A1 METHOD AND AN APPARATUS FOR COHERENCY CONTROL 有权
标题翻译：方法和设备的相似性控制
公开(公告)号：US20140082241A1
公开(公告)日：2014-03-20
申请号：US14000216
申请日：2011-02-28
申请人： Leonardo Vainsencher , Yaron P. Folk , Yuval Itkin
发明人： Leonardo Vainsencher , Yaron P. Folk , Yuval Itkin
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F12/0804 , G06F13/1663
摘要： The subject matter discloses a method for data coherency; the method comprising receiving an interrupt request for interrupting a CPU; wherein the interrupt request is from one of a plurality of modules; wherein the interrupt request notifying a writing instruction of a first data by the one of the plurality of modules to a shared memory; and wherein the shared memory is accessible to the plurality of modules through a shared bus; suspending the interrupt request; validating a completion of an execution of the writing instruction; wherein the validating is performed after the suspending; and resuming the interrupt request after the completion of the execution of the writing is validated, whereby to notify a to the CPU about the completion of the execution of the writing instruction.
摘要翻译：主题公开了一种数据一致性的方法; 该方法包括接收中断CPU的中断请求; 其中所述中断请求来自多个模块中的一个; 其中所述中断请求通知所述多个模块中的所述一个模块对共享存储器的第一数据的写入指令; 并且其中所述共享存储器通过共享总线可访问所述多个模块; 暂停中断请求; 验证完成写入指令的执行; 其中所述验证在所述暂停之后执行; 并且在完成执行写入之后恢复中断请求被确认，从而向CPU通知执行写入指令的完成。

7. 发明授权

US5999188A System and method for parametric surface representation from polygonal descriptions of arbitrary objects 失效
标题翻译：用于任意对象的多边形描述的参数表面表示的系统和方法
公开(公告)号：US5999188A
公开(公告)日：1999-12-07
申请号：US810256
申请日：1997-03-03
申请人： Nishit Kumar , Vineet Goel , Leonardo Vainsencher
发明人： Nishit Kumar , Vineet Goel , Leonardo Vainsencher
IPC分类号： G06T3/00 , G06T11/20 , G06T17/20 , G06T17/30
CPC分类号： G06T17/20
摘要： The present invention addresses the problem of describing an arbitrary object (up to user-defined limits) given a set of triangles with vertex normals describing the object. A novel method of successively merging traingles into larger and larger patches to compute a set of "as-few-as-possible" Bezier patches is presented. This method is not only applicable to arbitrary objects, but also aims at producing as few patches as possible depending on the geometry of the input object. Also presented are methods to enforce C.sup.0 - and C.sup.1 -continuity between a pair of patches B.sub.L (s,t) and B.sub.R (s,t), placed arbitrarily. The methods perturb the appropnate control points to achieve geometric continuities. For C.sup.0 -continuity the area of the hole between the patches is minimized by formulating the area as a series of linear programs, where the continuity has to be enforced across the adjacent boundary curves B.sub.L (1,t) and B.sub.R (0,t). Similarly, to enforce C.sup.1 -continuity the hole-area in tangential space is minimized.
摘要翻译：本发明解决了给定一组具有描述对象的顶点法线的三角形的任意对象（直到用户定义的限制）的问题。提出了一种将串联连续并入更大和更大的补丁以计算一组“尽可能少的”贝塞尔补丁的新颖方法。该方法不仅适用于任意对象，而且还可以根据输入对象的几何形状尽可能少地生成补丁。还提出了在任意放置的一对补丁BL（s，t）和BR（s，t）之间执行C0-和C1-连续性的方法。这些方法扰乱了适当的控制点来实现几何连续性。对于C0连续性，通过将区域配置为一系列线性程序，必须在相邻的边界曲线BL（1，t）和BR（0，t）之间执行连续性，使得补片之间的孔的面积最小化，。类似地，为了强制C1连续性，切向空间中的孔面积被最小化。

8. 发明授权

US07844880B2 Error correction for flash memory 有权
标题翻译：闪存的错误更正
公开(公告)号：US07844880B2
公开(公告)日：2010-11-30
申请号：US11985219
申请日：2007-11-13
申请人： Leonardo Vainsencher , Cahide Kiris
发明人： Leonardo Vainsencher , Cahide Kiris
IPC分类号： G11C29/00
CPC分类号： G06F11/1068
摘要： Systems and methods are disclosed to detect and correct errors in a flash memory using an error correction cache that provides error correction information by accessing data from a physical block number (PBN) of the flash memory; and if a data error occurred, applying error correction information stored in the cache corresponding to the accessed PBN to correct the data error.
摘要翻译：公开了系统和方法，以使用纠错高速缓存来检测和校正闪存中的错误，所述纠错高速缓存通过从闪存的物理块号（PBN）访问数据来提供纠错信息; 并且如果发生数据错误，则应用存储在与所访问的PBN相对应的高速缓存中的纠错信息来校正数据错误。

9. 发明申请

US20090160552A1 APPARATUS AND METHOD FOR CLASS D AMPLIFIER WITH SAMPLING RATE CONVERSION 有权
标题翻译：具有采样速率转换的D类放大器的装置和方法
公开(公告)号：US20090160552A1
公开(公告)日：2009-06-25
申请号：US12186232
申请日：2008-08-05
申请人： Leonardo Vainsencher
发明人： Leonardo Vainsencher
IPC分类号： H03F3/217
CPC分类号： H03F3/217
摘要： A class D amplifier is provided. The class D amplifier includes an interpolator, a sampling rate converter, a pulse width modulator, a sigma-delta modulator, and a pulse width modulation (PWM) pulse generator (PPG). The sampling rate converter interpolates the output of the interpolator such that the sampling rate converter up-samples the interpolator output by a factor that is greater than one and less than two. The pulse width modulator outputs a multi-bit digital signal. The sigma-delta modulator performs sigma-delta modulation on the pulse width modulator output, the order of the sigma-delta modulation is programmable, and the output of the sigma-delta modulator is a multi-bit, digital signal. At least one of the orders to which the sigma-delta modulator can be programmed is greater than two. The PPG provides a pulse signal such that the width of each pulse is based on the value of the sigma-delta modulator output.
摘要翻译：提供D类放大器。 D类放大器包括内插器，采样率转换器，脉冲宽度调制器，Σ-Δ调制器和脉冲宽度调制（PWM）脉冲发生器（PPG）。采样率转换器内插内插器的输出，使得采样率转换器将内插器输出上采样大于1且小于2的因子。脉冲宽度调制器输出多位数字信号。 Σ-Δ调制器在脉冲宽度调制器输出上执行Σ-Δ调制，Σ-Δ调制的顺序是可编程的，Σ-Δ调制器的输出是多位数字信号。 Σ-Δ调制器可编程的顺序中的至少一个大于2。 PPG提供脉冲信号，使得每个脉冲的宽度基于Σ-Δ调制器输出的值。

10. 发明授权

US06005624A System and method for performing motion compensation using a skewed tile storage format for improved efficiency 失效
标题翻译：使用倾斜瓦片存储格式进行运动补偿的系统和方法，以提高效率
公开(公告)号：US06005624A
公开(公告)日：1999-12-21
申请号：US772442
申请日：1996-12-20
申请人： Leonardo Vainsencher
发明人： Leonardo Vainsencher
IPC分类号： H04N5/92 , G06T9/00 , H04N7/26 , H04N7/32 , H04N7/36 , H04N7/50 , H04N7/12
CPC分类号： H04N19/433 , H04N19/423 , H04N19/51 , H04N19/61
摘要： An MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes motion compensation logic which analyzes motion vectors in an encoded frame of the MPEG stream and uses prior decoded reference blocks to recreate the data encoded by the motion vector. The MPEG decoder stores reference block data according to a novel skewed tile arrangement to minimize the maximum number of page crossings required in retrieving this data from the memory.
摘要翻译：用于解码视频序列的帧的MPEG解码器系统和方法。 MPEG解码器包括运动补偿逻辑，其分析MPEG流的编码帧中的运动矢量，并使用先前解码的参考块来重新创建由运动矢量编码的数据。 MPEG解码器根据新的倾斜瓦片布置来存储参考块数据，以最小化从存储器检索该数据所需的最大页面交叉数。

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