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1. 发明授权

US06518119B2 Strap with intrinsically conductive barrier 失效
标题翻译：带本征导电屏障
公开(公告)号：US06518119B2
公开(公告)日：2003-02-11
申请号：US09886065
申请日：2001-06-21
申请人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L29/945
摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of intrinsically conductive recrystallization barrier layers. The intrinsically conductive layers are preferably used adjacent to conductive strap features in trench capacitors to act as recrystallization barriers.
摘要翻译：通过产生和使用本征导电的再结晶阻挡层能够实现改进的可靠性和/或增加的组合选择的缩小结构。本征导电层优选与沟槽电容器中的导电带特征相邻地用作再结晶屏障。

2. 发明授权

US06236077B1 Trench electrode with intermediate conductive barrier layer 失效
标题翻译：带中间导电阻挡层的沟槽电极
公开(公告)号：US06236077B1
公开(公告)日：2001-05-22
申请号：US09295136
申请日：1999-04-20
申请人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10867 , H01L27/10861 , H01L29/66181 , H01L29/945
摘要： Reduced scale trench capacitor structures of improved reliability and decreased series resistance are enabled by the creation and use of conductive barrier layers at intermediate points in the trench electrode structure. The conductive barrier layer is preferably either an intrinsically conductive compound barrier or a quantum conductive barrier. The capacitor structures are preferably characterized by a lower electrode region of very high dopant concentration.
摘要翻译：通过在沟槽电极结构的中间点处产生和使用导电阻挡层，可实现提高可靠性和降低串联电阻的缩小沟槽电容器结构。导电阻挡层优选为本征导电化合物屏障或量子导电屏障。电容器结构的特征在于具有非常高掺杂剂浓度的下电极区域。

3. 发明授权

US06259129B1 Strap with intrinsically conductive barrier 失效
标题翻译：带本征导电屏障
公开(公告)号：US06259129B1
公开(公告)日：2001-07-10
申请号：US09295133
申请日：1999-04-20
申请人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10867 , H01L29/945
摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of intrinsically conductive recrystallization barrier layers. The intrinsically conductive layers are preferably used adjacent to conductive strap features in trench capacitors to act as recrystallization barriers.
摘要翻译：通过产生和使用本征导电的再结晶阻挡层能够实现改进的可靠性和/或增加的组合选择的缩小结构。本征导电层优选与沟槽电容器中的导电带特征相邻地用作再结晶屏障。

4. 发明授权

US06222218B1 DRAM trench 失效
标题翻译： DRAM沟槽
公开(公告)号：US06222218B1
公开(公告)日：2001-04-24
申请号：US09152835
申请日：1998-09-14
申请人： Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10861
摘要： The present invention relates to a process of fabricating semiconductor memory structures, particularly deep trench semiconductor memory devices wherein a temperature sensitive high dielectric constant material is incorporated into the storage node of the capacitor. Specifically, the present invention describes a process for forming deep trench storage capacitors after high temperature shallow trench isolation and gate conductor processing. This process allows for the incorporation of a temperature sensitive high dielectric constant material into the capacitor structure without causing decomposition of that material. Furthermore, the process of the present invention limits the extent of the buried-strap outdiffusion, thus improving the electrical characteristics of the array MOSFET.
摘要翻译：本发明涉及制造半导体存储器结构，特别是深沟槽半导体存储器件的工艺，其中将温度敏感的高介电常数材料并入电容器的存储节点中。具体地，本发明描述了在高温浅沟槽隔离和栅极导体处理之后形成深沟槽存储电容器的工艺。该过程允许将温度敏感的高介电常数材料并入电容器结构中而不会导致该材料的分解。此外，本发明的方法限制了埋层扩散的程度，从而改善阵列MOSFET的电特性。

5. 发明授权

US06352892B2 Method of making DRAM trench capacitor 失效
标题翻译：制造DRAM沟槽电容器的方法
公开(公告)号：US06352892B2
公开(公告)日：2002-03-05
申请号：US09764656
申请日：2001-01-17
申请人： Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10861
摘要： The present invention relates to a process of fabricating semiconductor memory structures, particularly deep trench semiconductor memory devices wherein a temperature sensitive high dielectric constant material is incorporated into the storage node of the capacitor. Specifically, the present invention describes a process for forming deep trench storage capacitors after high temperature shallow trench isolation and gate conductor processing. This process allows for the incorporation of a temperature sensitive high dielectric constant material into the capacitor structure without causing decomposition of that material. Furthermore, the process of the present invention limits the extent of the buried-strap outdiffusion, thus improving the electrical characteristics of the array MOSFET.
摘要翻译：本发明涉及制造半导体存储器结构，特别是深沟槽半导体存储器件的工艺，其中将温度敏感的高介电常数材料并入电容器的存储节点中。具体地，本发明描述了在高温浅沟槽隔离和栅极导体处理之后形成深沟槽存储电容器的工艺。该过程允许将温度敏感的高介电常数材料并入电容器结构中而不会导致该材料的分解。此外，本发明的方法限制了埋层扩散的程度，从而改善阵列MOSFET的电特性。

6. 发明授权

US06177696B1 Integration scheme enhancing deep trench capacitance in semiconductor integrated circuit devices 失效
标题翻译：集成方案增强了半导体集成电路器件中的深沟槽电容
公开(公告)号：US06177696B1
公开(公告)日：2001-01-23
申请号：US09133203
申请日：1998-08-13
申请人： Gary B. Bronner , Laertis Economikos , Rajarao Jammy , Byeongju Park , Carl J. Radens , Martin E. Schrems
发明人： Gary B. Bronner , Laertis Economikos , Rajarao Jammy , Byeongju Park , Carl J. Radens , Martin E. Schrems
IPC分类号： H01L2972
CPC分类号： H01L27/10861 , H01L21/32155 , H01L27/10829 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： A trench capacitor structure suitable for use in a semiconductor integrated circuit device and the process sequence used to form the structure. The trench capacitor provides increased capacitance by including a capacitor plate consisting of textured, hemispherical-grained silicon. The trench capacitor also includes a buried plate to reduce depletion of stored charge from the capacitor.
摘要翻译：适用于半导体集成电路器件的沟槽电容器结构和用于形成该结构的工艺顺序。沟槽电容器通过包括由纹理化的半球形硅组成的电容器板来提供增加的电容。沟槽电容器还包括掩埋板，以减少来自电容器的存储电荷的耗尽。

7. 发明授权

US07785959B2 Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效
标题翻译：在单元中并联连接沟槽电容器的多端口存储器制造方法
公开(公告)号：US07785959B2
公开(公告)日：2010-08-31
申请号：US12316748
申请日：2008-12-16
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.
摘要翻译：提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。

8. 发明授权

US07138685B2 Vertical MOSFET SRAM cell 失效
标题翻译：垂直MOSFET SRAM单元
公开(公告)号：US07138685B2
公开(公告)日：2006-11-21
申请号：US10318495
申请日：2002-12-11
申请人： Louis L. Hsu , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
发明人： Louis L. Hsu , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21/00
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/1104 , H01L27/1203
摘要： A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.
摘要翻译：形成SRAM单元装置的方法包括以下步骤。形成栅极FET晶体管并形成一对垂直下拉FET晶体管，其具有第一共同体和第一公共源，图案化为平坦绝缘体上形成平行岛的硅层。通过交叉耦合的反相器FET晶体管之间的上扩散来蚀刻，以形成将一对垂直下拉FET晶体管的上拉和下拉漏极区的上层平分的下拉隔离空间，隔离空间达到到共同的身体层。形成一对具有第二共同体和第二公共漏极的垂直上拉FET晶体管。然后，连接FET晶体管以形成SRAM单元。

9. 发明授权

US06759702B2 Memory cell with vertical transistor and trench capacitor with reduced burried strap 有权
标题翻译：具有垂直晶体管和沟槽电容器的存储单元，具有减少的挂带
公开(公告)号：US06759702B2
公开(公告)日：2004-07-06
申请号：US10261559
申请日：2002-09-30
申请人： Carl J. Radens , Ramachandra Divakaruni , Jack A. Mandelman
发明人： Carl J. Radens , Ramachandra Divakaruni , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L29/66181 , H01L29/945
摘要： A memory cell structure including a semiconductor substrate, a deep (e.g., longitudinal) trench in the semiconductor substrate, the deep trench having a plurality of sidewalls and a bottom, a buried strap along a sidewall of the deep trench, a storage capacitor at the bottom of the deep trench, a vertical transistor extending down the sidewall of the deep trench above the storage capacitor, the transistor having a diffusion extending in the plane of the substrate adjacent the deep trench, a collar oxide extending down another sidewall of the deep trench opposite the capacitor, shallow trench isolation regions extending along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends, a gate conductor extending within the deep trench, a wordline extending over the deep trench and connected to the gate conductor, and a bitline extending above the surface plane of the substrate having a contact to the diffusion between the shallow trench isolation regions. The deep trench has a perimeter in a direction normal to its depth, and the buried strap extends a distance along the perimeter, the distance being only within a range of 5% to 20% of the entire linear distance along the perimeter, and being less than one lithographic feature size. Preferably, the strap in a direction along the perimeter is curved and is disposed along only one corner of the perimeter. The structure is particularly useful for a sub-8F2 cell.
摘要翻译：一种存储单元结构，包括半导体衬底，半导体衬底中的深（例如，纵向）沟槽，深沟槽具有多个侧壁和底部，沿着深沟槽的侧壁的掩埋带，存储电容器深沟槽的底部，垂直晶体管，沿着存储电容器上方的深沟槽的侧壁向下延伸，晶体管具有在衬底的与深沟槽相邻的平面中延伸的扩散，从深沟槽的另一个侧壁延伸的环状氧化物与电容器相对的浅沟槽隔离区域沿垂直于垂直晶体管延伸的侧壁横向的衬底表面延伸，在深沟槽内延伸的栅极导体，延伸在深沟槽上并与栅极导体连接的字线以及在衬底的表面平面上方延伸的位线，该位线与浅沟槽iso之间的扩散接触国际地区。深沟槽在垂直于其深度的方向上具有周长，并且掩埋带沿着周边延伸一段距离，该距离仅在沿着周边的整个线性距离的5％至20％的范围内，并且更小比一个光刻特征尺寸。优选地，沿着周边的方向上的带子是弯曲的并且沿着周边的一个角部设置。该结构对于亚8F 2细胞特别有用。

10. 发明授权

US06720630B2 Structure and method for MOSFET with metallic gate electrode 有权
标题翻译：具有金属栅电极的MOSFET的结构和方法
公开(公告)号：US06720630B2
公开(公告)日：2004-04-13
申请号：US09867874
申请日：2001-05-30
申请人： Jack A. Mandelman , Oleg Gluschenkov , Carl J. Radens
发明人： Jack A. Mandelman , Oleg Gluschenkov , Carl J. Radens
IPC分类号： H01L2976
CPC分类号： H01L21/28247 , H01L29/4933 , H01L29/6653 , H01L29/66545 , H01L29/6659 , Y10S257/90
摘要： A method of forming a metal oxide semiconductor field effect transistor (MOSFET) having a metallic gate electrode that is protected with hanging sidewall spacers during a subsequent gate oxidation process is provided. A semiconductor structure formed by the inventive method is also provided. Specifically, the inventive semiconductor structure includes a semiconductor substrate comprising a patterned gate region formed atop a patterned gate dielectric, the patterned gate region includes at least a metallic gate electrode formed atop a polysilicon gate electrode; hanging sidewall spacers formed on an upper portion of the patterned gate region including the metallic gate electrode; and a thermal oxide layer formed on lower portions of patterned gate region including a portion of the polysilicon gate electrode, but not the metallic gate electrode.
摘要翻译：提供一种形成金属氧化物半导体场效应晶体管（MOSFET）的方法，该金属氧化物半导体场效应晶体管（MOSFET）具有金属栅电极，其在随后的栅极氧化处理期间被悬挂的侧壁间隔物保护。还提供了通过本发明方法形成的半导体结构。具体地，本发明的半导体结构包括半导体衬底，其包括形成在图案化栅极电介质上的图案化栅极区域，所述图案化栅极区域至少包括形成在多晶硅栅电极顶部的金属栅电极; 形成在包括金属栅极的图案化栅极区域的上部上的悬挂侧壁间隔物; 以及形成在图案化栅极区域的下部上的热氧化物层，其包括多晶硅栅电极的一部分而不是金属栅电极。

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