专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070287075A1 Mask arrangement, optical projection system and method for obtaining grating parameters and absorption properties of a diffractive optical element 审中-公开
$Mask arrangement, optical projection system and method for obtaining grating parameters and absorption properties of a diffractive optical element$
标题翻译：掩模布置，光学投影系统以及用于获得衍射光学元件的光栅参数和吸收特性的方法
公开(公告)号：US20070287075A1
公开(公告)日：2007-12-13
申请号：US11451618
申请日：2006-06-13
申请人： Rainer Pforr , Jens Reichelt , Mario Hennig , Thomas Mulders , Karsten Zeiler
发明人： Rainer Pforr , Jens Reichelt , Mario Hennig , Thomas Mulders , Karsten Zeiler
IPC分类号： G03B27/42 , G03F1/00
CPC分类号： G03F7/70433 , G03F1/62 , G03F7/70091 , G03F7/7015 , G03F7/70158
摘要： A mask arrangement or an optical projection system includes a diffractive optical element. The diffractive optical element includes grid sections having gratings with defined grating parameters and absorbing elements with defined absorption properties, wherein each grid section corresponds to a respective mask section with mask pattern elements. The diffractive optical element may correct dimension deviations of resist pattern elements obtained from the respective mask pattern elements, wherein the deviations are caused by dimension deviations of the mask pattern elements or by local deviations and defects of the projection system.
摘要翻译：掩模布置或光学投影系统包括衍射光学元件。衍射光学元件包括具有限定的光栅参数的光栅和具有限定的吸收特性的吸收元件的栅格部分，其中每个栅格部分对应于具有掩模图案元件的相应掩模部分。衍射光学元件可以校正从各个掩模图案元件获得的抗蚀剂图案元件的尺寸偏差，其中偏差是由掩模图案元件的尺寸偏差或投影系统的局部偏差和缺陷引起的。

2. 发明授权

US07339652B2 Apparatus for projecting a pattern into an image plane 有权
标题翻译：用于将图案投影到图像平面中的装置
公开(公告)号：US07339652B2
公开(公告)日：2008-03-04
申请号：US11339844
申请日：2006-01-26
申请人： Molela Moukara , Rainer Pforr , Thomas Muelders , Mario Hennig , Karsten Zeiler
发明人： Molela Moukara , Rainer Pforr , Thomas Muelders , Mario Hennig , Karsten Zeiler
IPC分类号： G03B27/54 , G03B27/72 , G03B27/42
CPC分类号： G03F7/70283 , G03F1/30 , G03F1/32 , G03F7/701 , G03F7/70108 , G03F7/70125
摘要： An improvement of the imaging quality with simultaneous transfer of line-space gratings and peripheral structures including a MUX space is achieved using a quadrupole illumination whose poles are formed in elongate fashion and whose longitudinal axes are arranged perpendicular to the orientation of the lines of the line-space grating arranged on a mask. The structure imaging of the line-space grating is improved with regard to contrast, MEEF, and process window, while the geometrical fidelity of the peripheral structure, in particular of the MUX space, is stabilized over a wide depth of field range.
摘要翻译：通过同时传输线间隔光栅和包括MUX空间的外围结构，可以实现成像质量的提高，其使用四极照明，其极以细长形式形成，其纵轴垂直于线的线的方向排列光栅布置在掩模上。相对于对比度，MEEF和处理窗口，线空间光栅的结构成像得到改善，而外围结构（特别是MUX空间）的几何保真度在宽的景深范围内是稳定的。

3. 发明申请

US20080042171A1 Transistor arrangement, sense-amplifier arrangement and methods of manufacturing the same via a phase shift mask 审中-公开
标题翻译：晶体管布置，读出放大器布置以及通过相移掩模制造它们的方法
公开(公告)号：US20080042171A1
公开(公告)日：2008-02-21
申请号：US11506205
申请日：2006-08-18
申请人： Sebastian Mosler , Mario Hennig , Karsten Zeiler , Thi Phuong Hoa Nguyen , Rainer Pforr , Jorg Thiele
发明人： Sebastian Mosler , Mario Hennig , Karsten Zeiler , Thi Phuong Hoa Nguyen , Rainer Pforr , Jorg Thiele
IPC分类号： H01L29/76 , H01L21/8234 , H01L27/108 , H01L21/8242
CPC分类号： H01L27/088 , G03F1/30 , H01L27/0207 , H01L27/10885
摘要： Methods of forming transistor arrangements using alternating phase shift masks are provided. The mask may include two parallel opaque lines, a first transparent section separating the opaque lines and a second transparent section in the rest. The second transparent section may shift the phase with respect to the first transparent section by 180 degree. A phase conflict occurs along an edge between the first and the second transparent sections. A semiconductor substrate is patterned via the mask and, from the opaque lines functional active areas of a transistor pair and from the phase conflict edge, thereby resulting in a parasitic area. A separation gate is provided that is capable of switching off a parasitic transistor being formed within the parasitic area. Channel widths may be stabilized and maximized within dense transistor arrangements, for example, in a multiplexer portion of a sense amplifier arrangement for memory cell arrays.
摘要翻译：提供了使用交替相移掩模形成晶体管布置的方法。掩模可以包括两个平行的不透明线，分隔不透明线的第一透明部分和其余部分中的第二透明部分。第二透明部分可以将相位相对于第一透明部分移位180度。沿着第一和第二透明部分之间的边缘发生相位冲突。通过掩模对半导体衬底进行图案化，并且从不透明线将晶体管对的功能有效区域和相冲突边缘图案化，由此导致寄生区域。提供了一种能够关闭在寄生区域内形成的寄生晶体管的分离栅极。通道宽度可以在致密晶体管布置中稳定和最大化，例如在用于存储单元阵列的读出放大器装置的多路复用器部分中。

4. 发明授权

US07393613B2 Set of at least two masks for the projection of structure patterns 失效
标题翻译：设置至少两个掩模用于投影结构图案
公开(公告)号：US07393613B2
公开(公告)日：2008-07-01
申请号：US10791763
申请日：2004-03-04
申请人： Wolfgang Dettmann , Jörg Thiele , Rainer Pforr , Mario Hennig , Karsten Zeiler
发明人： Wolfgang Dettmann , Jörg Thiele , Rainer Pforr , Mario Hennig , Karsten Zeiler
IPC分类号： G03F1/00 , G03F1/14
CPC分类号： G03F7/705 , G03F1/70 , G03F7/70466
摘要： A set of at least two masks, coordinated with one another, for the projection of structure patterns, into the same photosensitive layer arranged on a semiconductor wafer. The first mask includes a semitransparent or nontransparent first layer, which is arranged on a first substrate and in which at least one first opening is formed at a first position, the first opening having a first lateral dimension, which is greater than the resolution limit of a projection system for the projection of the structure patterns. The second mask includes a semitransparent or nontransparent second layer, which is arranged on a second substrate and in which at least one dummy structure assigned to the first opening is formed at a second position, the dummy structure having a second lateral dimension, which is smaller than the resolution limit of the projection system wherein the first position on the first mask corresponds to the second position on the second mask.
摘要翻译：一组至少两个掩模，用于将结构图案的投影彼此配合到设置在半导体晶片上的相同感光层中。第一掩模包括半透明或不透明的第一层，其布置在第一基板上，并且其中至少一个第一开口形成在第一位置，第一开口具有第一横向尺寸，该第一横向尺寸大于用于投影结构图案的投影系统。第二掩模包括半透明或不透明的第二层，其布置在第二基板上，并且其中在第二位置处形成分配给第一开口的至少一个虚拟结构，该虚拟结构具有第二横向尺寸，该第二横向尺寸较小比投影系统的分辨率极限，其中第一掩模上的第一位置对应于第二掩模上的第二位置。

5. 发明申请

US20060181691A1 Apparatus for projecting a pattern into an image plane 有权
标题翻译：用于将图案投影到图像平面中的装置
公开(公告)号：US20060181691A1
公开(公告)日：2006-08-17
申请号：US11339844
申请日：2006-01-26
申请人： Molela Moukara , Rainer Pforr , Thomas Muelders , Mario Hennig , Karsten Zeiler
发明人： Molela Moukara , Rainer Pforr , Thomas Muelders , Mario Hennig , Karsten Zeiler
IPC分类号： G03B27/54
CPC分类号： G03F7/70283 , G03F1/30 , G03F1/32 , G03F7/701 , G03F7/70108 , G03F7/70125
摘要： An improvement of the imaging quality with simultaneous transfer of line-space gratings and peripheral structures including a MUX space is achieved using a quadrupole illumination whose poles are formed in elongate fashion and whose longitudinal axes are arranged perpendicular to the orientation of the lines of the line-space grating arranged on a mask. The structure imaging of the line-space grating is improved with regard to contrast, MEEF, and process window, while the geometrical fidelity of the peripheral structure, in particular of the MUX space, is stabilized over a wide depth of field range.
摘要翻译：通过同时传输线间隔光栅和包括MUX空间的外围结构，可以实现成像质量的提高，其使用四极照明，其极以细长形式形成，其纵轴垂直于线的线的方向排列光栅布置在掩模上。相对于对比度，MEEF和处理窗口，线空间光栅的结构成像得到改善，而外围结构（特别是MUX空间）的几何保真度在宽的景深范围内是稳定的。

6. 发明申请

US20060183258A1 Imaging system and method for producing semiconductor structures on a wafer by imaging a mask on the wafer with a dipole diaphragm 审中-公开
标题翻译：通过用偶极子膜片将晶片上的掩模成像在晶片上制造半导体结构的成像系统和方法
公开(公告)号：US20060183258A1
公开(公告)日：2006-08-17
申请号：US11334941
申请日：2006-01-19
申请人： Mario Hennig , Wolfram Koestler , Molela Moukara , Joerg Thiele , Thorsten Winkler , Karsten Zeiler
发明人： Mario Hennig , Wolfram Koestler , Molela Moukara , Joerg Thiele , Thorsten Winkler , Karsten Zeiler
IPC分类号： G06F17/50 , H01L21/00
CPC分类号： G03F7/70433 , G03F1/00 , G03F7/70125
摘要： An imaging system having a dipole diaphragm (2) having two diaphragm openings (2b) arranged one behind the other in a dipole axis (y), and a mask having mask structures (20, 23) is used for producing semiconductor structures (10′, 13′) on a wafer (15′) by imaging the mask (25) onto the wafer (15′). The dipole diaphragm (2) is provided for the imaging of the mask (25), and the mask (25), for producing main semiconductor structures (10; 10′) on the wafer (15′), has main mask structures (20) parallel to an imaging axis (x) running perpendicular to the dipole axis (y). At least one connecting mask structure (23′) oriented obliquely with respect to the dipole axis (y) at least in sections is formed on the mask (25), which structure connects at least two main mask structures (20) to one another.
摘要翻译：一种具有偶极子（2）的成像系统，其具有在偶极轴（y）中一个彼此排列的两个隔膜开口（2b）和具有掩模结构（20,23）的掩模，用于制造半导体结构 '，13'）通过将掩模（25）成像到晶片（15'）上而在晶片（15'）上。提供偶极隔膜（2）用于掩模（25）的成像，并且用于在晶片（15'）上制造主半导体结构（10; 10'）的掩模（25）具有主掩模结构（20 ）平行于垂直于偶极轴（y）延伸的成像轴（x）。在掩模（25）上形成至少一部分相对于偶极轴（y）倾斜定向的至少一个连接掩模结构（23'），该结构将至少两个主掩模结构（20）彼此连接。

7. 发明申请

US20060177773A1 Method for producing semiconductor patterns on a wafer 审中-公开
标题翻译：在晶片上制造半导体图案的方法
公开(公告)号：US20060177773A1
公开(公告)日：2006-08-10
申请号：US11335152
申请日：2006-01-19
申请人： Mario Hennig , Wolfram Koestler , Molela Moukara , Joerg Thiele , Thorsten Winkler , Karsten Zeiler
发明人： Mario Hennig , Wolfram Koestler , Molela Moukara , Joerg Thiele , Thorsten Winkler , Karsten Zeiler
IPC分类号： G03F7/00
CPC分类号： G03F7/70466 , G03F1/70 , G03F7/701 , G03F7/70425
摘要： A method is used to produce semiconductor patterns (10′, 13′) on a wafer (15′). For this purpose, a mask (25) and a dipole aperture (2) with two aperture openings (2b) arranged behind one another in a dipole axis (y) are used. The mask (25) is imaged on the wafer (15′) by means of the dipole aperture (2) and, by the imaging of the mask (25) on the wafer (15′), main semiconductor patterns (10′) are produced which are aligned perpendicularly to the dipole axis (y) and in parallel with an imaging axis (x). A second mask (35) with at least one connecting mask pattern (33) is imaged on the wafer (15′) by means of a second aperture (6), as a result of which a connecting semiconductor pattern (13) is produced on the wafer (15′), by means of which at least two of the main semiconductor patterns (10′) are connected to one another.
摘要翻译：使用一种方法来在晶片（15'）上产生半导体图案（10'，13'）。为此，使用具有在偶极轴（y）中彼此相邻布置的两个开口开口（2b）的掩模（25）和偶极孔（2）。通过偶极孔（2）将掩模（25）成像在晶片（15'）上，并且通过在晶片（15'）上的掩模（25）的成像，主半导体图案（10'）产生的垂直于偶极轴（y）并与成像轴（x）平行排列。具有至少一个连接掩模图案（33）的第二掩模（35）通过第二孔（6）被成像在晶片（15'）上，结果在其上产生连接半导体图案（13）所述晶片（15'）通过所述晶片（15'）中的至少两个所述主半导体图案（10'）彼此连接。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式