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1. 发明授权

US07277808B1 Process parameter based I/O timing programmability using electrical fuse elements 有权
标题翻译：使用电熔丝元件的基于工艺参数的I / O定时可编程性
公开(公告)号：US07277808B1
公开(公告)日：2007-10-02
申请号：US11381425
申请日：2006-05-03
申请人： Raguram Damodaran , Manjeri Krishnan , Todd Beck
发明人： Raguram Damodaran , Manjeri Krishnan , Todd Beck
IPC分类号： G06F19/00
CPC分类号： G06F17/5045 , G06F2217/62 , G06F2217/84
摘要： Electrical fuses (eFuses) are applied to the task of achieving very tightly controlled Input-Output (I/O) timing specifications. The I/O timing is made programmable and subject to adjustment as part of wafer probe testing. The techniques of parametric adjustment presented are based upon what is commonly referred to as clock skewing or clock tuning. The invention describes methods to select the clock skewing on a die-to-die basis based on functional testing with the actual parametric limits imposed on parameters of interest. The results associated with each die form the basis for hard-programming the selected clock skew value into the die via electrical fuses.
摘要翻译：电气保险丝（eFuses）适用于实现非常严格控制的输入输出（I / O）时序规范的任务。 I / O定时可编程，可作为晶圆探针测试的一部分进行调整。所提出的参数调整技术是基于通常称为时钟偏移或时钟调谐的。本发明描述了基于功能测试来选择基于管芯到管芯的时钟偏移的方法，该功能测试具有施加在感兴趣的参数上的实际参数限制。与每个芯片相关的结果构成了通过电熔丝将所选择的时钟偏移值硬编程到芯片中的基础。

2. 发明申请

US20050075830A1 Process parameter based I/O timing programmability using electrical fuse elements 有权
标题翻译：使用电熔丝元件的基于工艺参数的I / O定时可编程性
公开(公告)号：US20050075830A1
公开(公告)日：2005-04-07
申请号：US10679724
申请日：2003-10-06
申请人： Raguram Damodaran , Manjeri Krishnan , Todd Beck
发明人： Raguram Damodaran , Manjeri Krishnan , Todd Beck
IPC分类号： G01R31/317 , G04G15/00 , G06F15/00 , H01L21/82 , H01L21/822 , H01L27/04
CPC分类号： G01R31/31725 , G01R31/31726
摘要： Electrical fuses (eFuses) are applied to the task of achieving very tightly controlled Input-Output (I/O) timing specifications. The I/O timing is made programmable and subject to adjustment as part of wafer probe testing. The techniques of parametric adjustment presented are based upon what is commonly referred to as clock skewing or clock tuning. The invention describes methods to select the clock skewing on a die-to-die basis based on functional testing with the actual parametric limits imposed on parameters of interest. The results associated with each die form the basis for hard-programming the selected clock skew value into the die via electrical fuses.
摘要翻译：电气保险丝（eFuses）适用于实现非常严格控制的输入输出（I / O）时序规范的任务。 I / O定时可编程，可作为晶圆探针测试的一部分进行调整。所提出的参数调整技术是基于通常称为时钟偏移或时钟调谐的。本发明描述了基于功能测试来选择基于管芯到管芯的时钟偏移的方法，该功能测试具有施加在感兴趣的参数上的实际参数限制。与每个芯片相关的结果构成了通过电熔丝将所选择的时钟偏移值硬编程到芯片中的基础。

3. 发明授权

US07158902B2 Process parameter based I/O timing programmability using electrical fuse elements 有权
公开(公告)号：US07158902B2
公开(公告)日：2007-01-02
申请号：US10679724
申请日：2003-10-06
申请人： Raguram Damodaran , Manjeri Krishnan , Todd Beck
发明人： Raguram Damodaran , Manjeri Krishnan , Todd Beck
IPC分类号： G06F19/00
CPC分类号： G01R31/31725 , G01R31/31726
摘要： Electrical fuses (eFuses) are applied to the task of achieving very tightly controlled Input-Output (I/O) timing specifications. The I/O timing is made programmable and subject to adjustment as part of wafer probe testing. The techniques of parametric adjustment presented are based upon what is commonly referred to as clock skewing or clock tuning. The invention describes methods to select the clock skewing on a die-to-die basis based on functional testing with the actual parametric limits imposed on parameters of interest. The results associated with each die form the basis for hard-programming the selected clock skew value into the die via electrical fuses.

4. 发明授权

US08904115B2 Cache with multiple access pipelines 有权
标题翻译：具有多路访问管道的缓存
公开(公告)号：US08904115B2
公开(公告)日：2014-12-02
申请号：US13212895
申请日：2011-08-18
申请人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
发明人： Abhijeet Ashok Chachad , Raguram Damodaran , Jonathan (Son) Hung Tran , Timothy David Anderson , Sanjive Agarwala
IPC分类号： G06F12/00 , G06F7/483 , G06F12/02 , G06F1/32 , G06F9/30 , H03M13/35 , H03M13/29 , G06F11/10 , H03K19/00 , H03K21/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.
摘要翻译：并行流水线用于访问共享内存。通过处理器通过第一管线访问共享存储器以从共享存储器访问缓存的数据。通过存储器访问单元通过第二管线访问共享存储器以访问共享存储器。维持第一组标签以供第一管线使用以控制对高速缓冲存储器的访问，而第二组标签被维护供第二管道用于访问共享存储器。在每个流水线检查其相应的一组标签之后，执行仲裁以访问第一流水线中的事务请求的高速缓冲存储器和第二流水线中的事务请求。

5. 发明授权

US08560896B2 Priority based exception mechanism for multi-level cache controller 有权
标题翻译：多级缓存控制器基于优先级的异常机制
公开(公告)号：US08560896B2
公开(公告)日：2013-10-15
申请号：US13245164
申请日：2011-09-26
申请人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
发明人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
IPC分类号： G06F11/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is an exception priority arbitration unit which prioritizes memory access permission fault and data exception signals according to a fixed hierarchy if received during a same cycle. A CPU memory access permission fault is prioritized above a DMA memory access permission fault of a direct memory access permission fault. Any memory access permission fault is prioritized above a data exception signal. A non-correctable data exception signal is prioritized above a correctable data exception signal.
摘要翻译：本发明是一种异常优先仲裁单元，其在相同的周期内被接收时，根据固定层次来优先考虑存储器访问许可故障和数据异常信号。 CPU内存访问权限错误优先于直接内存访问许可故障的DMA内存访问权限错误。任何存储器访问权限故障都优先于数据异常信号。不可修正的数据异常信号优先于可纠正的数据异常信号。

6. 发明授权

US08532247B2 Integer and half clock step division digital variable clock divider 有权
标题翻译：整数和半时钟分频数字可变时钟分频器
公开(公告)号：US08532247B2
公开(公告)日：2013-09-10
申请号：US13247265
申请日：2011-09-28
申请人： Ramakrishnan Venkatasubramanian , Anthony Lell , Raguram Damodaran
发明人： Ramakrishnan Venkatasubramanian , Anthony Lell , Raguram Damodaran
IPC分类号： H03K21/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A clock divider divides a high speed input clock signal by an odd, even or fractional divide ratio. The clock divider receives a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates a fractional divide ratio when one and an integral divide ratio when zero. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. The clock divider synthesizes one period of an output clock signal in response to each assertion of the count indicator for a fractional divide ratio and synthesizes one period of the output clock signal in response to two assertions of the count indicator for an integral divide ratio.
摘要翻译：时钟分频器将高速输入时钟信号除以奇数，偶数或分数分频比。时钟分频器接收代表分频比N的除法因子值F，其中N可以是奇数或偶数整数。一个分数指示符表示当零和一个积分分频比为零时的分数分频比。当N为偶数时，每N / 2个输入时钟周期，计数指示器被置位。当N为奇数时，计数指示灯交替显示N / 2个输入时钟周期，然后1 + N / 2个输入时钟周期。时钟分频器响应于分数分频比的计数指示器的每个断言而合成输出时钟信号的一个周期，并响应于积分分频比的计数指示符的两个断言来合成输出时钟信号的一个周期。

7. 发明申请

US20120191913A1 Distributed User Controlled Multilevel Block and Global Cache Coherence with Accurate Completion Status 有权
标题翻译：分布式用户控制的多级块和全局缓存一致性与准确的完成状态
公开(公告)号：US20120191913A1
公开(公告)日：2012-07-26
申请号：US13240479
申请日：2011-09-22
申请人： Raguram Damodaran , Abhijeet A. Chachad
发明人： Raguram Damodaran , Abhijeet A. Chachad
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention permits user controlled cache coherence operations with the flexibility to do these operations on all levels of cache together or each level independently. In the case of an all level operation, the user does not have to monitor and sequence each phase of the operation. This invention also provides a way for users to track completion of these operations. This is critical for multi-core/multi-processor devices. Multiple cores may be accessing the end point and the user/application needs to be able to identify when the operation from one core is complete, before permitting other cores access that data or code.
摘要翻译：本发明允许用户控制的高速缓存一致性操作，具有灵活性，可以在所有级别的高速缓存上独立地进行这些操作。在所有级别操作的情况下，用户不必监视和排序操作的每个阶段。本发明还提供了一种用于跟踪这些操作完成的方式。这对于多核/多处理器设备至关重要。在允许其他核心访问该数据或代码之前，多个核心可能正在访问终点，并且用户/应用程序需要能够识别来自一个核心的操作何时完成。

8. 发明申请

US20120079155A1 Interleaved Memory Access from Multiple Requesters 审中-公开
标题翻译：多个请求者的交织内存访问
公开(公告)号：US20120079155A1
公开(公告)日：2012-03-29
申请号：US13239065
申请日：2011-09-21
申请人： Raguram Damodaran , Naveen Bhoria
发明人： Raguram Damodaran , Naveen Bhoria
IPC分类号： G06F13/362
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A shared memory system having multiple banks is coupled to a set of requesters. Separate arbitration and control logic is provided for each bank, such that each bank can be accessed individually. The separate arbitration logics individually arbitrate transaction requests targeted to each bank of the memory. Access is granted to each bank on each access cycle to a highest priority request for each bank, such that more than one transaction request may be granted access to the memory on a same access cycle. A wide transaction request that has a transaction width that is wider than a width of one bank is divided into a plurality of divided requests.
摘要翻译：具有多个存储体的共享存储器系统耦合到一组请求器。为每个银行提供单独的仲裁和控制逻辑，以便可以单独访问每个银行。单独的仲裁逻辑单独仲裁针对每个存储器组的事务请求。每个访问周期向每个银行授予访问权限，以便为每个银行提供最高优先级的请求，以便可以在同一访问周期内允许多个事务请求访问存储器。具有比一个银行的宽度更宽的交易宽度的广泛的交易请求被划分为多个划分的请求。

9. 发明申请

US20090172487A1 Multiple pBIST Controllers 有权
标题翻译：多个pBIST控制器
公开(公告)号：US20090172487A1
公开(公告)日：2009-07-02
申请号：US11967148
申请日：2007-12-29
申请人： Raguram Damodaran , Umang Bharatkumar Thakkar , John David Sayre
发明人： Raguram Damodaran , Umang Bharatkumar Thakkar , John David Sayre
IPC分类号： G06F11/27
CPC分类号： G06F11/27
摘要： A system on a single integrated circuit chip (SoC) includes a plurality of operational circuits to be tested. A plurality of programmable built-in self-test (pBIST) controllers is connected to respective ones of the plurality of operational circuits in a manner that allows the pBIST controllers to test the respective operation circuits in parallel. An interface is connected to each of the plurality of pBIST controllers for connection to an external tester to facilitate programming of each of the plurality of pBIST controllers by the external tester, such that the plurality of pBIST controllers are operable to test the plurality of operational circuits in parallel and report the results of the parallel tests to the external tester, thereby reducing test time.
摘要翻译：单个集成电路芯片（SoC）上的系统包括要测试的多个操作电路。多个可编程内置自检（pBIST）控制器以允许pBIST控制器并行测试各个操作电路的方式连接到多个操作电路中的相应的一个操作电路。接口连接到多个pBIST控制器中的每一个，用于连接到外部测试器，以便外部测试器对多个pBIST控制器中的每一个进行编程，使得多个pBIST控制器可操作以测试多个操作电路并行并行测试结果报告给外部测试仪，从而减少测试时间。

10. 发明授权

US07324392B2 ROM-based memory testing 有权
标题翻译：基于ROM的内存测试
公开(公告)号：US07324392B2
公开(公告)日：2008-01-29
申请号：US11422726
申请日：2006-06-07
申请人： Ananthakrishnan Ramamurti , Raguram Damodaran
发明人： Ananthakrishnan Ramamurti , Raguram Damodaran
IPC分类号： G11C7/00 , G11C29/00 , G06F11/00 , G01R31/28
CPC分类号： G11C29/16 , G11C17/14
摘要： This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each test set stored in the pBIST ROM into read/write registers. These registers are memory mapped readable/writable. A configuration register has an algorithm bit and a data bit which determines whether the corresponding algorithm or data is loaded from the pBIST ROM. The pBIST unit includes another configuration register having one bit corresponding to each possible test set stored in the pBIST ROM. The pBIST unit runs a test set if the corresponding bit in the configuration register has a first digital state.
摘要翻译：本发明独特地划分用于存储程序和数据信息的pBIST ROM。 pBIST单元选择性地将存储在pBIST ROM中的每个测试集合的算法和数据，仅算法或数据加载到读/写寄存器中。这些寄存器是可读写的内存映射。配置寄存器具有算法位和数据位，用于确定对应的算法或数据是否从pBIST ROM加载。 pBIST单元包括具有与存储在pBIST ROM中的每个可能测试集相对应的一个位的另一个配置寄存器。如果配置寄存器中的相应位具有第一数字状态，则pBIST单元运行测试集。

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