专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07608913B2 Noise isolation between circuit blocks in an integrated circuit chip 有权
标题翻译：集成电路芯片中电路块之间的噪声隔离
公开(公告)号：US07608913B2
公开(公告)日：2009-10-27
申请号：US11360285
申请日：2006-02-23
申请人： Radu M. Secareanu , Suman K. Banerjee , Olin L. Hartin
发明人： Radu M. Secareanu , Suman K. Banerjee , Olin L. Hartin
IPC分类号： H01L23/58 , H01L23/62 , H01L29/00
CPC分类号： H01L29/0649 , H01L21/761 , H01L21/762 , H01L21/765 , H01L21/823481 , H01L29/0619
摘要： An integrated circuit includes a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region formed surrounding the p-well block region for providing noise isolation between the first circuit block and the second circuit block.
摘要翻译：集成电路包括由于在衬底的区域中形成的低掺杂浓度而具有高电阻率的p阱块区域，用于在第一电路块和第二电路块之间提供噪声隔离。集成电路还包括围绕p阱块区域形成的保护区域，用于在第一电路块和第二电路块之间提供噪声隔离。

2. 发明授权

US09048110B2 Noise isolation between circuit blocks in an integrated circuit chip 有权
标题翻译：集成电路芯片中电路块之间的噪声隔离
公开(公告)号：US09048110B2
公开(公告)日：2015-06-02
申请号：US13802006
申请日：2013-03-13
申请人： Radu M. Secareanu , Suman K. Banerjee , Olin L. Hartin
发明人： Radu M. Secareanu , Suman K. Banerjee , Olin L. Hartin
IPC分类号： H01L29/00 , H01L23/552 , H01L29/06 , H01L21/761 , H01L21/762 , H01L21/765 , H01L21/8234
CPC分类号： H01L29/0649 , H01L21/761 , H01L21/762 , H01L21/765 , H01L21/823481 , H01L29/0619
摘要： An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.
摘要翻译：集成电路包括在衬底的区域中形成的低掺杂浓度的p阱块区域，用于在第一电路块和第二电路块之间提供噪声隔离。集成电路还包括保护区域和接地的高掺杂区域，用于提供额外的噪声隔离。

3. 发明申请

US20090302440A1 NOISE ISOLATION BETWEEN CIRCUIT BLOCKS IN AN INTEGRATED CIRCUIT CHIP 审中-公开
标题翻译：集成电路芯片中的电路块之间的噪声隔离
公开(公告)号：US20090302440A1
公开(公告)日：2009-12-10
申请号：US12512616
申请日：2009-07-30
申请人： Radu M. Secareanu , Suman K. Banerjee , Olin L. Hartin
发明人： Radu M. Secareanu , Suman K. Banerjee , Olin L. Hartin
IPC分类号： H01L23/62 , H01L23/552
CPC分类号： H01L29/0649 , H01L21/761 , H01L21/762 , H01L21/765 , H01L21/823481 , H01L29/0619
摘要： An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.
摘要翻译：集成电路包括在衬底的区域中形成的低掺杂浓度的p阱块区域，用于在第一电路块和第二电路块之间提供噪声隔离。集成电路还包括保护区域和接地的高掺杂区域，用于提供额外的噪声隔离。

4. 发明授权

US07138686B1 Integrated circuit with improved signal noise isolation and method for improving signal noise isolation 有权
标题翻译：具有改进的信号噪声隔离的集成电路和用于改善信号噪声隔离的方法
公开(公告)号：US07138686B1
公开(公告)日：2006-11-21
申请号：US11142433
申请日：2005-05-31
申请人： Suman K. Banerjee , Enrique Ferrer , Olin L. Hartin , Radu M. Secareanu
发明人： Suman K. Banerjee , Enrique Ferrer , Olin L. Hartin , Radu M. Secareanu
IPC分类号： H01L29/76
CPC分类号： H01L27/0248 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A system-on chip (SOC) (100) and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks (120, 220) and ESD protected pads (302, 304, 306, 308, 310, 312, and 314). A VDD isolation pad (302) is connected to an N well ring (124) of the first noise sensitive circuit (120) to collect noise from the substrate (110) and isolate the circuit from the P well region (112). A ground protected pad (304) is connected to an isolated P well (126) of a first noise sensitive circuit (120). The ground pad (304) collects noise from the isolated P well (126) and sends it to ground. A dedicated ground isolation pad (306) is connected to a P well ring (224) of a second noise sensitive circuit (220). The dedicated ground isolation pad (306) collects noise from the P well ring (224) and sends it to ground. The dedicated ground isolation pad (306) and the ground pad (304) collect noise that would normally propagate between the first and second noise sensitive circuits (120, 220) and additional circuits that share the same substrate (110).
摘要翻译：一种片上系统（SOC）（100）以及分离SOC中的噪声的方法，包括多个噪声敏感电路块（120,220）和ESD保护焊盘（302,304,306,308,310,312,312）和314）。 VDD隔离焊盘（302）连接到第一噪声敏感电路（120）的N阱环（124），以从基板（110）收集噪声，并将电路与P阱区域（112）隔离。接地保护焊盘（304）连接到第一噪声敏感电路（120）的隔离P阱（126）。接地焊盘（304）从隔离的P阱（126）收集噪声并将其发送到地面。专用接地隔离垫（306）连接到第二噪声敏感电路（220）的P阱环（224）。专用接地隔离垫（306）从P阱环（224）收集噪声并将其发送到地面。专用接地隔离焊盘（306）和接地焊盘（304）收集正常地在第一和第二噪声敏感电路（120,220）之间传播的噪声以及共享相同衬底（110）的附加电路。

5. 发明授权

US07683483B2 Electronic device with connection bumps 有权
标题翻译：带连接凸块的电子设备
公开(公告)号：US07683483B2
公开(公告)日：2010-03-23
申请号：US11671048
申请日：2007-02-05
申请人： Radu M. Secareanu , Suman K. Banerjee , Olin L. Hartin , Sandra J. Wipf
发明人： Radu M. Secareanu , Suman K. Banerjee , Olin L. Hartin , Sandra J. Wipf
IPC分类号： H01L23/48 , H01L29/00
CPC分类号： H01L24/14 , H01L24/13 , H01L24/16 , H01L2224/13099 , H01L2224/14133 , H01L2224/16 , H01L2224/17519 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , H01L2224/29099 , H01L2224/0401
摘要： Flip-chip electronic devices (40, 70, 80, 90) employ bumps (42, 72, 82) for coupling to an external substrate. Device cells (43, 73, 83, 93) and bumps (42, 72, 82) are preferably arranged in clusters (46) where four bumps (42, 72, 82) substantially surround each device cell (43, 73, 83, 93) or form a cross with the device cell (43, 73, 83, 93) at the intersection of the cross. The bumps (42, 72, 82) are desirably spaced apart by the minimum allowable bump (42, 72, 82) pitch (Lm). Typically, each device cell (43, 73, 83, 93) contains one or more active device regions (44, 74, 86, 96) depending on the overall function. Complex devices (40, 70) are formed by an X-Y array of the clusters (46), where adjacent clusters (46) may share bumps (43, 73, 83, 93) and/or device cells (43, 73, 83, 93). In a preferred embodiment, the bumps (42, 82) form the outer perimeter (48) of the device (40, 80, 90). The maximum device temperature and overall noise is reduced.
摘要翻译：倒装芯片电子器件（40,70,80,90）使用用于耦合到外部衬底的凸块（42,72,82）。装置单元（43,73,83,93）和凸块（42,72,82）优选地布置成簇（46），其中四个凸块（42,72,82）基本上围绕每个器件单元（43,73,83） 93）或与十字交叉点处的设备单元（43,73,83,93）形成十字。凸起（42,72,82）期望地间隔开最小允许凸起（42,72,82）间距（Lm）。通常，取决于整个功能，每个设备单元（43,43,83,93）包含一个或多个有源器件区域（44,47,86,96）。复数器件（40,70）由簇（46）的XY阵列形成，其中相邻的簇（46）可共享凸块（43,43,83,93）和/或器件单元（43,43,83， 93）。在优选实施例中，凸块（42,82）形成装置（40,80,90）的外周边（48）。最大器件温度和总噪声降低。

6. 发明申请

US20130207229A1 NOISE ISOLATION BETWEEN CIRCUIT BLOCKS IN AN INTEGRATED CIRCUIT CHIP 有权
公开(公告)号：US20130207229A1
公开(公告)日：2013-08-15
申请号：US13802006
申请日：2013-03-13
申请人： Radu M. Secareanu , Suman K. Banerjee , Olin L. Hartin
发明人： Radu M. Secareanu , Suman K. Banerjee , Olin L. Hartin
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/761 , H01L21/762 , H01L21/765 , H01L21/823481 , H01L29/0619
摘要： An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.

7. 发明申请

US20080185686A1 ELECTRONIC DEVICE WITH CONNECTION BUMPS 有权
标题翻译：具有连接件的电子设备
公开(公告)号：US20080185686A1
公开(公告)日：2008-08-07
申请号：US11671048
申请日：2007-02-05
申请人： Radu M. Secareanu , Suman K. Banerjee , Olin L. Hartin , Sandra J. Wipf
发明人： Radu M. Secareanu , Suman K. Banerjee , Olin L. Hartin , Sandra J. Wipf
IPC分类号： H01L23/48 , H01L29/00
CPC分类号： H01L24/14 , H01L24/13 , H01L24/16 , H01L2224/13099 , H01L2224/14133 , H01L2224/16 , H01L2224/17519 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , H01L2224/29099 , H01L2224/0401
摘要： Flip-chip electronic devices (40, 70, 80, 90) employ bumps (42, 72, 82) for coupling to an external substrate. Device cells (43, 73, 83, 93) and bumps (42, 72, 82) are preferably arranged in clusters (46) where four bumps (42, 72, 82) substantially surround each device cell (43, 73, 83, 93) or form a cross with the device cell (43, 73, 83, 93) at the intersection of the cross. The bumps (42, 72, 82) are desirably spaced apart by the minimum allowable bump (42, 72, 82) pitch (Lm). Typically, each device cell (43, 73, 83, 93) contains one or more active device regions (44, 74, 86, 96) depending on the overall function. Complex devices (40, 70) are formed by an X-Y array of the clusters (46), where adjacent clusters (46) may share bumps (43, 73, 83, 93) and/or device cells (43, 73, 83, 93). In a preferred embodiment, the bumps (42, 82) form the outer perimeter (48) of the device (40, 80, 90). The maximum device temperature and overall noise is reduced.
摘要翻译：倒装芯片电子器件（40,70,80,90）使用用于耦合到外部衬底的凸块（42,72,82）。装置单元（43,73,83,93）和凸块（42,72,82）优选地布置成簇（46），其中四个凸块（42,72,82）基本上围绕每个器件单元（43,73,83） 93）或与十字交叉点处的设备单元（43,73,83,93）形成十字。凸起（42,72,82）期望地间隔开最小允许凸起（42,72,82）间距（L SUB）。通常，取决于整个功能，每个设备单元（43,43,83,93）包含一个或多个有源器件区域（44,47,86,96）。复数器件（40,70）由簇（46）的XY阵列形成，其中相邻的簇（46）可共享凸块（43,43,83,93）和/或器件单元（43,43,83， 93）。在优选实施例中，凸块（42,82）形成装置（40,80,90）的外周边（48）。最大器件温度和总噪声降低。

8. 发明授权

US08957496B2 Integrated circuit chip with discontinuous guard ring 有权
标题翻译：具有不连续保护环的集成电路芯片
公开(公告)号：US08957496B2
公开(公告)日：2015-02-17
申请号：US13864729
申请日：2013-04-17
申请人： Qiang Li , Olin L. Hartin , Sateh Jalaleddine , Radu M. Secareanu , Michael J. Zunino
发明人： Qiang Li , Olin L. Hartin , Sateh Jalaleddine , Radu M. Secareanu , Michael J. Zunino
IPC分类号： H01L21/70 , H01L21/76 , H01L27/02
CPC分类号： H01L27/0203 , H01L21/76 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L23/585 , H01L23/645 , H01L27/08 , H01L28/10 , H01L29/402 , H01L29/404 , H01L2924/0002 , H01L2924/00
摘要： An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.
摘要翻译：电子设备包括半导体衬底，设置在半导体衬底中并由半导体衬底支撑并包括电感器的电路块以及围绕电路块的不连续噪声隔离保护环。不连续的噪声隔离保护环包括由半导体衬底支撑的金属环和设置在半导体衬底中的环形区域，具有掺杂剂浓度水平并且电耦合到金属环，以抑制半导体衬底中的噪声达到电路。金属环具有第一间隙，并且环形区域具有第二间隙。

9. 发明授权

US07834428B2 Apparatus and method for reducing noise in mixed-signal circuits and digital circuits 有权
标题翻译：用于降低混合信号电路和数字电路噪声的装置和方法
公开(公告)号：US07834428B2
公开(公告)日：2010-11-16
申请号：US11680430
申请日：2007-02-28
申请人： Radu M. Secareanu , Olin L. Hartin , Emre Salman
发明人： Radu M. Secareanu , Olin L. Hartin , Emre Salman
IPC分类号： H01L27/06 , H01L23/64
CPC分类号： H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus (200) includes a metal-oxide-semiconductor field-effect transistor (MOSFET) (210). MOSFET (210) includes a doped substrate (2210) with a source formed proximate a substrate tie (2224) and a substrate tie (2250) adjacent substrate (2210). A ground rail (255) is coupled to the source and substrate tie (2224), and a ground rail (285) is coupled to substrate tie (2250). Ground rails (255) and (285) are configured to be coupled to different ground networks (250 and 280). One method includes producing a model of a semiconductor device including a standard semiconductor cell (710). The semiconductor cell is identified as a noise-sensitive or a noise-producing semiconductor cell (720), and the semiconductor cell is replaced with a corresponding noise-aware semiconductor cell (730).
摘要翻译：提供了用于降低混合信号和数字电路中的噪声的装置和方法。一种装置（200）包括金属氧化物半导体场效应晶体管（MOSFET）（210）。 MOSFET（210）包括掺杂衬底（2210），源极靠近衬底接合端（2224）和与衬底（2210）相邻的衬底接头（2250）。接地导轨（255）耦合到源极和衬底连接件（2224），并且接地导轨（285）耦合到衬底连接件（2250）。地线（255）和（285）被配置为耦合到不同的地面网络（250和280）。一种方法包括制造包括标准半导体单元（710）的半导体器件的模型。半导体单元被识别为噪声敏感或产生噪声的半导体单元（720），并且半导体单元被相应的噪声感知半导体单元（730）替代。

10. 发明申请

US20140312457A1 INTEGRATED CIRCUIT CHIP WITH DISCONTINUOUS GUARD RING 有权
标题翻译：集成电路芯片与不连续的保护环
公开(公告)号：US20140312457A1
公开(公告)日：2014-10-23
申请号：US13864729
申请日：2013-04-17
申请人： Qiang Li , Olin L. Hartin , Sateh Jalaleddine , Radu M. Secareanu , Michael J. Zunino
发明人： Qiang Li , Olin L. Hartin , Sateh Jalaleddine , Radu M. Secareanu , Michael J. Zunino
IPC分类号： H01L27/02 , H01L21/76
CPC分类号： H01L27/0203 , H01L21/76 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L23/585 , H01L23/645 , H01L27/08 , H01L28/10 , H01L29/402 , H01L29/404 , H01L2924/0002 , H01L2924/00
摘要： An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.
摘要翻译：电子设备包括半导体衬底，设置在半导体衬底中并由半导体衬底支撑并包括电感器的电路块以及围绕电路块的不连续噪声隔离保护环。不连续的噪声隔离保护环包括由半导体衬底支撑的金属环和设置在半导体衬底中的环形区域，具有掺杂剂浓度水平并且电耦合到金属环，以抑制半导体衬底中的噪声达到电路。金属环具有第一间隙，并且环形区域具有第二间隙。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式