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1. 发明申请

US20120228014A1 CIRCUITIZED SUBSTRATE WITH INTERNAL THIN FILM CAPACITOR AND METHOD OF MAKING SAME 审中-公开
标题翻译：具有内薄膜电容器的电路衬底及其制造方法
公开(公告)号：US20120228014A1
公开(公告)日：2012-09-13
申请号：US13042578
申请日：2011-03-08
申请人： Rabindra N. Das , Mark D. Poliks , Voya R. Markovich , Peter A. Moschak
发明人： Rabindra N. Das , Mark D. Poliks , Voya R. Markovich , Peter A. Moschak
IPC分类号： H05K1/16 , B05D5/12
CPC分类号： H05K1/162 , H01G4/33 , H01G4/38 , H05K1/0231 , H05K3/4608 , H05K2201/017 , H05K2201/0179
摘要： A circuitized substrate for use in such electrical structures as information handling systems wherein the substrate includes a capacitive substrate as part thereof. The capacitive substrate includes a thin film layer of capacitive material strategically positioned on a conductive layer relative to added electrically conductive elements to in turn provide a plurality of internal capacitors within the final circuitized substrate during operation thereof. A method of making such a circuitized substrate is also provided.
摘要翻译：一种用于诸如信息处理系统的电气结构中的电路化基板，其中所述基板包括作为其一部分的电容基板。电容性衬底包括相对于添加的导电元件策略性地定位在导电层上的电容材料薄层，从而在其操作期间在最终电路化衬底内提供多个内部电容器。还提供了制造这种电路化基板的方法。

2. 发明授权

US08685284B2 Conducting paste for device level interconnects 有权
标题翻译：用于器件级互连的导电膏
公开(公告)号：US08685284B2
公开(公告)日：2014-04-01
申请号：US12884657
申请日：2010-09-17
申请人： Rabindra N. Das , Roy H. Magnuson , Mark D. Poliks , Voya R. Markovich
发明人： Rabindra N. Das , Roy H. Magnuson , Mark D. Poliks , Voya R. Markovich
IPC分类号： H01B1/00 , H01B1/22 , H01B1/02
CPC分类号： H01B1/22 , H01L2224/81 , Y10T29/49117
摘要： A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.
摘要翻译：导电糊和形成用于器件级互连的糊的方法。导电浆料含有80-95％范围内的金属负载，可用于制造五微米器件级互连。通过混合两种不同的导电浆料制成导电糊料，即使在最终固化后，每个糊料仍将其微量级独立富含区域保持在混合糊料中。一种糊状物含有至少一种低熔点合金，另一种糊状物含有贵金属填料如金或银薄片。通常，小于5微米的平均片尺寸适用于五微米互连。然而，对于5微米互连，优选1微米或更小的银薄片和LMP混合物。最终混合物中基于LMP的糊剂的量优选为20-50重量％。纳米微膏实施例显示良好的电收率（81％）和低接触电阻。

3. 发明申请

US20120257343A1 CONDUCTIVE METAL MICRO-PILLARS FOR ENHANCED ELECTRICAL INTERCONNECTION 审中-公开
标题翻译：导电金属微支架，用于增强电气互连
公开(公告)号：US20120257343A1
公开(公告)日：2012-10-11
申请号：US13082502
申请日：2011-04-08
申请人： Rabindra N. Das , Konstantinos I. Papathomas , Mark D. Poliks , Voya R. Markovich
发明人： Rabindra N. Das , Konstantinos I. Papathomas , Mark D. Poliks , Voya R. Markovich
IPC分类号： G06F1/16 , H05K3/00 , H05K1/09 , G03F7/20 , H01B1/02 , B82Y99/00
CPC分类号： H05K3/4614 , B82Y10/00 , B82Y30/00 , H05K2203/0307 , H05K2203/061
摘要： A method of forming a circuitized substrate for use in electronic packages. A substrate layer is provided that has a copper pad on a surface. A conductive seed layer and a photoresist layer are placed on the surface. The photoresist is developed and conductive material is placed within the developed features and a second conductive material placed on the first conductive material. The photoresist and conductive seed layer are removed to leave a micro-pillar array. The joining and lamination of two circuitized substrate layers utilizes the micro-pillar array for the electrical connection of the circuitized substrate layers.
摘要翻译：一种形成用于电子封装的电路化基板的方法。提供了在表面上具有铜垫的基底层。导电种子层和光致抗蚀剂层被放置在表面上。光致抗蚀剂被显影并且导电材料被放置在显影特征内并且第二导电材料放置在第一导电材料上。去除光致抗蚀剂和导电种子层以留下微柱阵列。两个电路化衬底层的接合和叠层利用微柱阵列用于电路化衬底层的电连接。

4. 发明申请

US20120068326A1 ANTI-TAMPER MICROCHIP PACKAGE BASED ON THERMAL NANOFLUIDS OR FLUIDS 失效
标题翻译：基于热纳米脂或流体的防篡改微型包装
公开(公告)号：US20120068326A1
公开(公告)日：2012-03-22
申请号：US12884421
申请日：2010-09-17
申请人： Rabindra N. Das , Voya R. Markovich , James J. McNamara, JR. , Mark D. Poliks
发明人： Rabindra N. Das , Voya R. Markovich , James J. McNamara, JR. , Mark D. Poliks
IPC分类号： H01L23/22
CPC分类号： H01L23/42 , H01L23/573 , H01L24/13 , H01L24/16 , H01L24/29 , H01L2224/13101 , H01L2224/16225 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/29344 , H01L2224/29369 , H01L2224/29387 , H01L2224/29393 , H01L2224/73204 , H01L2224/73253 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2924/00014
摘要： A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.
摘要翻译：防篡改微芯片封装包含流体或纳米流体填充的胶囊，通道或储存器，其中单独或组合的流体可以在尝试逆向工程化时通过蚀刻，烧结或热破坏来破坏电路。当流体填充的空腔被切掉以便对微芯片进行详细检查时，释放流体。可以将纳米流体用于烧结过程，并且还可以增加用于管芯热管理的流体的热导率。通孔和微通孔可以并入设计中以通过改善流体/芯片接触来增加电路破坏功效。也可以使用热界面材料来促进芯片冷却。

5. 发明授权

US08288857B2 Anti-tamper microchip package based on thermal nanofluids or fluids 失效
标题翻译：基于热纳米流体或流体的防篡改微芯片封装
公开(公告)号：US08288857B2
公开(公告)日：2012-10-16
申请号：US12884421
申请日：2010-09-17
申请人： Rabindra N. Das , Voya R. Markovich , James J. McNamara, Jr. , Mark D. Poliks
发明人： Rabindra N. Das , Voya R. Markovich , James J. McNamara, Jr. , Mark D. Poliks
IPC分类号： H01L23/22 , H01L23/12
CPC分类号： H01L23/42 , H01L23/573 , H01L24/13 , H01L24/16 , H01L24/29 , H01L2224/13101 , H01L2224/16225 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/29344 , H01L2224/29369 , H01L2224/29387 , H01L2224/29393 , H01L2224/73204 , H01L2224/73253 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2924/00014
摘要： A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.
摘要翻译：防篡改微芯片封装包含流体或纳米流体填充的胶囊，通道或储存器，其中单独或组合的流体可以在尝试逆向工程化时通过蚀刻，烧结或热破坏来破坏电路。当流体填充的空腔被切掉以便对微芯片进行详细检查时，释放流体。可以将纳米流体用于烧结过程，并且还可以增加用于管芯热管理的流体的热导率。通孔和微通孔可以并入设计中以通过改善流体/芯片接触来增加电路破坏功效。也可以使用热界面材料来促进芯片冷却。

6. 发明申请

US20120069531A1 CONDUCTING PASTE FOR DEVICE LEVEL INTERCONNECTS 有权
标题翻译：用于设备级互连的导电胶
公开(公告)号：US20120069531A1
公开(公告)日：2012-03-22
申请号：US12884657
申请日：2010-09-17
申请人： Rabindra N. Das , Roy H. Magnuson , Mark D. Poliks , Voya R. Markovich
发明人： Rabindra N. Das , Roy H. Magnuson , Mark D. Poliks , Voya R. Markovich
IPC分类号： H05K7/00 , H01B1/02 , H01B1/22 , H01R43/00
CPC分类号： H01B1/22 , H01L2224/81 , Y10T29/49117
摘要： A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.
摘要翻译：导电糊和形成用于器件级互连的糊的方法。导电浆料含有80-95％范围内的金属负载，可用于制造五微米器件级互连。通过混合两种不同的导电浆料制成导电糊料，即使在最终固化后，每个糊料仍将其微量级独立富含区域保持在混合糊料中。一种糊状物含有至少一种低熔点合金，另一种糊状物含有贵金属填料如金或银薄片。通常，小于5微米的平均片尺寸适用于五微米互连。然而，对于5微米互连，优选1微米或更小的银薄片和LMP混合物。最终混合物中基于LMP的糊剂的量优选为20-50重量％。纳米微膏实施例显示良好的电收率（81％）和低接触电阻。

7. 发明授权

US07025607B1 Capacitor material with metal component for use in circuitized substrates, circuitized substrate utilizing same, method of making said circuitized substrate, and information handling system utilizing said circuitized substrate 失效
标题翻译：具有用于电路化基板的金属部件的电容器材料，利用其的电路化基板，制造所述电路化基板的方法以及利用所述电路化基板的信息处理系统
公开(公告)号：US07025607B1
公开(公告)日：2006-04-11
申请号：US11031074
申请日：2005-01-10
申请人： Rabindra N. Das , John M. Lauffer , Voya R. Markovich , Mark D. Poliks
发明人： Rabindra N. Das , John M. Lauffer , Voya R. Markovich , Mark D. Poliks
IPC分类号： H01R4/58
CPC分类号： H01G4/206 , H01L2224/16 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/0102 , H01L2924/01025 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H05K1/162 , H05K3/0023 , H05K2201/0187 , H05K2201/0209 , H05K2201/0215 , H05K2201/0257 , H01L2224/0401
摘要： A material for use as part of an internal capacitor within a circuitized substrate includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ferroelectric ceramic component, the ferroelectric ceramic component nano-particles having a particle size substantially in the range of between about 0.01 microns and about 0.9 microns and a surface within the range of from about 2.0 to about 20 square meters per gram. A circuitized substrate adapted for using such a material and capacitor therein and a method of making such a substrate are also provided. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) are also provided.
摘要翻译：用作电路化基板内的内部电容器的一部分的材料包括聚合物树脂和一定数量的纳米粉末，其包括至少一种金属组分和至少一种铁电陶瓷组分的混合物，所述铁电陶瓷组分纳米颗粒具有基本上在约0.01微米至约0.9微米范围内的粒度和约2.0至约20平方米每克的表面。还提供了适于在其中使用这种材料和电容器的电路化基板和制造这种基板的方法。还提供电气组件（基板和至少一个电气部件）和信息处理系统（例如，个人计算机）。

8. 发明授权

US08446707B1 Circuitized substrate with low loss capacitive material and method of making same 有权
标题翻译：具有低损耗电容性材料的电路化基板及其制造方法
公开(公告)号：US08446707B1
公开(公告)日：2013-05-21
申请号：US13269770
申请日：2011-10-10
申请人： Rabindra N. Das , Konstantinos I. Papathomas , Voya R. Markovich , James J. McNamara
发明人： Rabindra N. Das , Konstantinos I. Papathomas , Voya R. Markovich , James J. McNamara
IPC分类号： H01G4/06
CPC分类号： H01G4/33 , H01G7/06 , H05K1/0231 , H05K3/429 , H05K3/4602
摘要： A low loss capacitance and low loss insulating dielectric material consisting of a thermosetting resin, thermoplastic resin, a cross-linker, and containing a quantity of ferroelectric ceramic nano-particles of barium titanate within. The combined low loss insulating dielectric layer and a low loss capacitive layer resulting from the material allows one continuous layer that can form internal capacitors and permit the modifying the dielectric thickness between signal layers for impedance matching within a layer of substrate. More significantly, the applied layer of low loss capacitive materials can simultaneously act as a capacitor as well as a dielectric for separation of signal layers.
摘要翻译：由热固性树脂，热塑性树脂，交联剂组成的含有钛酸钡的铁电陶瓷纳米粒子的低损耗电容和低损耗绝缘介电材料。组合的低损耗绝缘电介质层和由该材料产生的低损耗电容层允许一个连续的层可以形成内部电容器并且允许改变信号层之间的介电厚度以在衬底层内进行阻抗匹配。更重要的是，所应用的低损耗电容材料层可以同时充当电容器以及用于分离信号层的电介质。

9. 发明申请

US20120201006A1 ELECTRONIC PACKAGE WITH THERMAL INTERPOSER AND METHOD OF MAKING SAME 失效
标题翻译：具有热插入器的电子封装及其制造方法
公开(公告)号：US20120201006A1
公开(公告)日：2012-08-09
申请号：US13022654
申请日：2011-02-08
申请人： Voya R. Markovich , Rabindra N. Das , Frank D. Egitto , James J. McNamara, JR.
发明人： Voya R. Markovich , Rabindra N. Das , Frank D. Egitto , James J. McNamara, JR.
IPC分类号： H05K7/20 , H05K3/36
CPC分类号： H05K7/1061 , H01L23/473 , H01L23/49833 , H01L23/5389 , H01L2924/0002 , H05K1/0203 , H05K2201/10378 , H01L2924/00
摘要： An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates while including at least one electrical component (e.g., a power module) substantially therein to provide even further operational capabilities for the resulting package.
摘要翻译：具有夹在其间的插入件的两个电路化基板的电子封装件，所述插入器将基板电气互连，同时包括至少一个电气部件（例如，功率模块），其基本上在其中，以为所得到的封装提供甚至进一步的操作能力。

10. 发明申请

US20120160547A1 CORELESS LAYER BUILDUP STRUCTURE 有权
标题翻译：无线层建筑结构
公开(公告)号：US20120160547A1
公开(公告)日：2012-06-28
申请号：US12764993
申请日：2010-04-22
申请人： Timothy Antesberger , Rabindra N. Das , Frank D. Egitto , Voya R. Markovich , William E. Wilson
发明人： Timothy Antesberger , Rabindra N. Das , Frank D. Egitto , Voya R. Markovich , William E. Wilson
IPC分类号： H05K1/03 , H05K1/02 , H05K1/09 , H05K1/00
CPC分类号： H05K3/462 , H05K1/167 , H05K3/4069 , H05K3/4623 , H05K3/4632 , H05K2203/0191 , H05K2203/061 , H05K2203/063
摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin.
摘要翻译：一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。

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