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1. 发明申请

US20180240513A1 SEMICONDUCTOR STORAGE DEVICE 审中-公开
公开(公告)号：US20180240513A1
公开(公告)日：2018-08-23
申请号：US15957263
申请日：2018-04-19
申请人： Renesas Electronics Corporation
发明人： Toshiaki SANO , Ken SHIBATA , Shinji TANAKA , Makoto YABUUCHI , Noriaki MAEDA
IPC分类号： G11C11/419 , G11C7/12
CPC分类号： G11C11/419 , G11C7/12 , G11C8/16 , G11C11/412 , G11C11/418
摘要： A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

2. 发明申请

US20180069010A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180069010A1
公开(公告)日：2018-03-08
申请号：US15795624
申请日：2017-10-27
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Ken SHIBATA , Yuta YANAGITANI
IPC分类号： H01L27/11 , H01L21/8238 , H01L29/10 , G11C5/14 , G11C11/412 , G11C11/417 , G11C11/418 , G11C11/419 , H01L29/423 , H01L27/02 , H01L27/092 , H01L29/06 , H01L29/08
CPC分类号： H01L27/1104 , G11C5/14 , G11C11/412 , G11C11/417 , G11C11/418 , G11C11/419 , H01L21/823892 , H01L27/0207 , H01L27/092 , H01L27/1116 , H01L29/0684 , H01L29/0847 , H01L29/1079 , H01L29/42356
摘要： A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+ (DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.

3. 发明申请

US20140140145A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20140140145A1
公开(公告)日：2014-05-22
申请号：US14164214
申请日：2014-01-26
申请人： Renesas Electronics Corporation
发明人： Binhaku TARUISHI , Hiroki MIYASHITA , Ken SHIBATA , Masashi HORIGUCHI
IPC分类号： G11C7/10
CPC分类号： G11C7/1084 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/1096
摘要： A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.
摘要翻译：在对存储器单元进行的写入操作的指令的接收之后，数据输入缓冲器从非活动状态改变为活动状态。输入缓冲器是具有例如基于SSTL的接口规格的差分输入缓冲器，其通过接通电源开关而使其通过电流流动并接收信号而进入激活状态，同时紧随着小的变化小振幅信号。由于只有当提供了对存储器单元的写操作指令时，输入缓冲器才进入活动状态，所以在提供指令之前预先使输入缓冲器无效，从而减少浪费的功耗。在另一方面，通过在从写入命令发布到下一个命令发布的时间段内从主动状态变为非活动状态来降低功耗。

4. 发明申请

US20170092352A1 SEMICONDUCTOR STORAGE DEVICE 有权
公开(公告)号：US20170092352A1
公开(公告)日：2017-03-30
申请号：US15373783
申请日：2016-12-09
申请人： Renesas Electronics Corporation
发明人： Toshiaki SANO , Ken SHIBATA , Shinji TANAKA , Makoto YABUUCHI , Noriaki MAEDA
IPC分类号： G11C11/419 , G11C11/418
CPC分类号： G11C11/419 , G11C7/12 , G11C8/16 , G11C11/412 , G11C11/418
摘要： A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

5. 发明申请

US20160300597A1 SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY 有权
公开(公告)号：US20160300597A1
公开(公告)日：2016-10-13
申请号：US15190263
申请日：2016-06-23
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Kiyotada FUNANE , Ken SHIBATA , Yasuhisa SHIMAZAKI
IPC分类号： G11C5/06
CPC分类号： G11C11/417 , G11C5/02 , G11C5/06 , G11C7/1075 , G11C8/16 , G11C11/412 , G11C11/413 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

6. 发明申请

US20160118389A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20160118389A1
公开(公告)日：2016-04-28
申请号：US14990262
申请日：2016-01-07
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Ken SHIBATA , Yuta YANAGITANI
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , G11C5/14 , G11C11/412 , G11C11/417 , G11C11/418 , G11C11/419 , H01L21/823892 , H01L27/0207 , H01L27/092 , H01L27/1116 , H01L29/0684 , H01L29/0847 , H01L29/1079 , H01L29/42356
摘要： A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.
摘要翻译：具有高自由度布置的半导体器件具有第一部分AR1，其中多个p型阱PW和n型阱NW沿着X轴方向交替布置成彼此相邻。多个井PW的公共供电区域（ARP2）布置在一侧，以将AR1插入Y轴方向，并且用于多个井NW的公共供电区域（ARN2）布置在另一边。在PW阱的供电区域（ARP2）中，形成具有沿X轴方向延伸的细长形状的p +型供电扩散层P +（DFW）。在AR1中布置有沿X轴方向延伸以跨越PW和NW阱之间的边界的多个栅极层GT，并且相应地形成多个MIS晶体管。

7. 发明申请

US20130258741A1 SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY 有权
公开(公告)号：US20130258741A1
公开(公告)日：2013-10-03
申请号：US13900127
申请日：2013-05-22
申请人： Renesas Electronics Corporation
发明人： Kiyotada FUNANE , Ken SHIBATA , Yasuhisa SHIMAZAKI
IPC分类号： G11C5/02
CPC分类号： G11C11/417 , G11C5/02 , G11C5/06 , G11C7/1075 , G11C8/16 , G11C11/412 , G11C11/413 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

8. 发明申请

US20170236576A1 SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY 有权
公开(公告)号：US20170236576A1
公开(公告)日：2017-08-17
申请号：US15583093
申请日：2017-05-01
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Kiyotada FUNANE , Ken SHIBATA , Yasuhisa SHIMAZAKI
IPC分类号： G11C11/417
CPC分类号： G11C11/417 , G11C5/02 , G11C5/06 , G11C7/1075 , G11C8/16 , G11C11/412 , G11C11/413 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

9. 发明申请

US20160240246A1 SEMICONDUCTOR STORAGE DEVICE 有权
公开(公告)号：US20160240246A1
公开(公告)日：2016-08-18
申请号：US15134981
申请日：2016-04-21
申请人： Renesas Electronics Corporation
发明人： Toshiaki SANO , Ken SHIBATA , Shinji TANAKA , Makoto YABUUCHI , Noriaki MAEDA
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/12 , G11C8/16 , G11C11/412 , G11C11/418
摘要： A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

10. 发明申请

US20150003140A1 SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY 有权
标题翻译：具有多个存储器的半导体器件
公开(公告)号：US20150003140A1
公开(公告)日：2015-01-01
申请号：US14490235
申请日：2014-09-18
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Kiyotada FUNANE , Ken SHIBATA , Yasuhisa SHIMAZAKI
IPC分类号： G11C5/02
CPC分类号： G11C11/417 , G11C5/02 , G11C5/06 , G11C7/1075 , G11C8/16 , G11C11/412 , G11C11/413 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.
摘要翻译：能够扩大噪声容限的半导体器件。例如，在存储单元MC与第一端口的字线WLA和第二端口的字线WLB连接的存储区域中，并且多个存储单元MC以矩阵形状配置，线以WLA0，WLB0，WLB1，WLA1，WLA2的顺序排列。此外，使WLA-WLA和WLB-WLB之间的间距d2小于WLA-WLB之间的间距d1。这样，相同端口的字线以某一字线的两侧之一的间距d2设置，而不同端口的字线以间距d1设置。

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