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1. 发明申请

US20210105425A1 PROGRAMMABLE DIGITAL TDI EO/IR SCANNING FOCAL PLANE ARRAY WITH MULTIPLE SELECTABLE TDI SUB-BANKS 有权
公开(公告)号：US20210105425A1
公开(公告)日：2021-04-08
申请号：US17091689
申请日：2020-11-06
申请人： RAYTHEON COMPANY
发明人： Steven Botts , Bryan W. Kean , Richard J. Peralta , John L. Vampola , Micky R. Harris
IPC分类号： H04N5/369 , H04N5/33 , H04N5/359 , H04N5/372 , H04N5/378
摘要： A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.

2. 发明申请

US20160134820A1 METHOD AND APPARATUS FOR INCREASING PIXEL SENSITIVITY AND DYNAMIC RANGE 有权
标题翻译：增加像素灵敏度和动态范围的方法和装置
公开(公告)号：US20160134820A1
公开(公告)日：2016-05-12
申请号：US14536733
申请日：2014-11-10
申请人： RAYTHEON COMPANY
发明人： Bryan W. Kean , John L. Vampola
IPC分类号： H04N5/355 , H04N5/3745
CPC分类号： H04N5/3559 , H04N5/3745 , H04N5/37452
摘要： According to one aspect, embodiments herein provide a unit cell comprising a photodiode, a MOSCap having an input node coupled to the photodiode, a reset switch selectively coupled between the MOSCap and a reset voltage, and a transistor coupled to the input node of the MOSCap, wherein, in a first mode of operation of the unit cell, the reset switch is configured in an open state and charge generated by light incident on the photodiode accumulates at the input node of the MOSCap in response to voltage at the input node being less than a threshold voltage, and wherein, in a second mode of operation of the unit cell, the reset switch is configured in the open state and the charge generated by the light incident on the photodiode accumulates on the MOSCap in response to the voltage at the input node being greater than the threshold voltage.
摘要翻译：根据一个方面，本文的实施例提供了一种单元单元，其包括光电二极管，具有耦合到光电二极管的输入节点的MOSCap，选择性地耦合在MOSCap和复位电压之间的复位开关以及耦合到MOSCap的输入节点的晶体管，其中在所述单电池的第一操作模式中，所述复位开关被配置为处于断开状态，并且响应于所述输入节点处的电压而在所述MOSCap的输入节点处累积的入射到所述光电二极管上的光产生的电荷累积并且其中，在所述单位电池的第二工作模式中，所述复位开关被配置为处于打开状态，并且由入射到所述光电二极管上的光产生的电荷响应于所述MOSCap处的电压积累在所述MOSCap上输入节点大于阈值电压。

3. 发明授权

US11356622B1 Single-ended capacitive trans-impedance amplifier (CTIA) unit cell for two-color applications 有权
公开(公告)号：US11356622B1
公开(公告)日：2022-06-07
申请号：US17214751
申请日：2021-03-26
申请人： RAYTHEON COMPANY
发明人： Bryan W. Kean , John L. Vampola , Joshua J. Cantrell
IPC分类号： H04N5/353 , H04N5/374 , H04N5/378 , H03F3/08 , H03F3/45 , H03F1/00 , H03F1/02 , H03F1/22 , H04N5/3745
摘要： An image capturing device is provided, which includes a capacitive trans-impedance amplifier (CTIA) unit cell. The CTIA unit cell includes an image detector and a switching network. The image detector is configured to detect light having a first color and light having a second color different from the first color, and to generate a photocurrent in response to detecting the light. The switching network includes a CTIA switch, a CTIA low reset switch, and a CTIA high-reset biasing switch. The CTIA switch sets a first reset level of the CTIA unit cell to a first voltage in response invoking a first switching state of the CTIA low-reset switch and sets a second reset level of the CTIA to a second voltage greater than the first voltage level in response to invoking a second switching state of the CTIA low-reset switch.

4. 发明授权

US08686766B2 Read out integrated circuit 有权
标题翻译：读出集成电路
公开(公告)号：US08686766B2
公开(公告)日：2014-04-01
申请号：US13764483
申请日：2013-02-11
申请人： Raytheon Company
发明人： Kanon Liu , Bryan W. Kean , James F. Asbrock
IPC分类号： H03L7/00
CPC分类号： H03F3/68 , G01C3/08 , H03F3/087 , H03F3/45475 , H03F2200/264 , H03F2200/78
摘要： According to one embodiment, a circuit comprises a Capacitive Trans-Impedance Amplifier (CTIA) configured to receive a current pulse at an input and convert the current pulse to a voltage step. The voltage step is directed to a first signal path and a second signal path. When the voltage step exceeds a first threshold, the first signal path directs an enable pulse to the second signal path. The second signal path generates an output pulse when the voltage step exceeds a second threshold and the enable pulse is enabled. The second signal path comprises a first, a second, and a third amplifier to increase detection of the voltage step by the second signal path.
摘要翻译：根据一个实施例，电路包括电容反阻抗放大器（CTIA），其被配置为在输入处接收电流脉冲并将电流脉冲转换成电压阶跃。电压步骤被引导到第一信号路径和第二信号路径。当电压步长超过第一阈值时，第一信号路径将使能脉冲引导到第二信号路径。第二信号路径当电压步长超过第二阈值时产生输出脉冲，使能脉冲使能。第二信号路径包括第一，第二和第三放大器，以增加第二信号路径对电压步进的检测。

5. 发明申请

US20140062602A1 READ OUT INTEGRATED CIRCUIT 有权
标题翻译：读出集成电路
公开(公告)号：US20140062602A1
公开(公告)日：2014-03-06
申请号：US13764483
申请日：2013-02-11
申请人： Raytheon Company
发明人： Kanon Liu , Bryan W. Kean , James F. Asbrock
IPC分类号： H03F3/68
CPC分类号： H03F3/68 , G01C3/08 , H03F3/087 , H03F3/45475 , H03F2200/264 , H03F2200/78
摘要： According to one embodiment, a circuit comprises a Capacitive Trans-Impedance Amplifier (CTIA) configured to receive a current pulse at an input and convert the current pulse to a voltage step. The voltage step is directed to a first signal path and a second signal path. When the voltage step exceeds a first threshold, the first signal path directs an enable pulse to the second signal path. The second signal path generates an output pulse when the voltage step exceeds a second threshold and the enable pulse is enabled. The second signal path comprises a first, a second, and a third amplifier to increase detection of the voltage step by the second signal path.
摘要翻译：根据一个实施例，电路包括电容反阻抗放大器（CTIA），其被配置为在输入处接收电流脉冲并将电流脉冲转换成电压阶跃。电压步骤被引导到第一信号路径和第二信号路径。当电压步长超过第一阈值时，第一信号路径将使能脉冲引导到第二信号路径。第二信号路径当电压步长超过第二阈值时产生输出脉冲，使能脉冲使能。第二信号路径包括第一，第二和第三放大器，以增加第二信号路径对电压步进的检测。

6. 发明授权

US09774802B2 Method and apparatus for increasing pixel sensitivity and dynamic range 有权
公开(公告)号：US09774802B2
公开(公告)日：2017-09-26
申请号：US14536733
申请日：2014-11-10
申请人： RAYTHEON COMPANY
发明人： Bryan W. Kean , John L. Vampola
IPC分类号： H04N5/355 , H04N5/3745
CPC分类号： H04N5/3559 , H04N5/3745 , H04N5/37452
摘要： According to one aspect, embodiments herein provide a unit cell comprising a photodiode, a MOSCap having an input node coupled to the photodiode, a reset switch selectively coupled between the MOSCap and a reset voltage, and a transistor coupled to the input node of the MOSCap, wherein, in a first mode of operation of the unit cell, the reset switch is configured in an open state and charge generated by light incident on the photodiode accumulates at the input node of the MOSCap in response to voltage at the input node being less than a threshold voltage, and wherein, in a second mode of operation of the unit cell, the reset switch is configured in the open state and the charge generated by the light incident on the photodiode accumulates on the MOSCap in response to the voltage at the input node being greater than the threshold voltage.

7. 发明申请

US20150288907A1 METHOD AND SYSTEM FOR MANAGING DEFECTS IN FOCAL PLANE ARRAYS USING REDUNDANT COMPONENTS 审中-公开
标题翻译：管理使用冗余组件的正面平面阵列缺陷的方法和系统
公开(公告)号：US20150288907A1
公开(公告)日：2015-10-08
申请号：US14244032
申请日：2014-04-03
申请人： RAYTHEON COMPANY
发明人： John L. Vampola , Micky R. Harris , Bryan W. Kean , Steven E. Botts
IPC分类号： H04N5/3745 , H04N5/376 , H01L27/146
CPC分类号： H04N5/3745 , H01L27/14643 , H04N5/367 , H04N5/3765 , H04N5/378 , H04N17/002
摘要： A focal plane array having: an imaging array section, comprising: an array of electromagnetic radiation detectors; and an address section providing outputs from selectively enabled detectors. The imaging array section comprises a plurality of circuit blocks, each one of the circuit blocks having a primary circuit and a redundant circuit. Test circuitry is for provided for supplying test signals to test each one of the primary circuits and determining whether a response from the test signals is proper or improper and for storing in the test circuitry in response to such determining select signals associated with each one of the tested circuit blocks. An array controller is provided for, during a subsequent normal operating mode, providing timing pulses to the address section wherein the address section selectively enables the detectors using either the primary or redundant circuits in the plurality of circuit blocks selectively in accordance with the stored select signals.
摘要翻译： 1.一种焦平面阵列，具有：成像阵列部，包括：电磁辐射检测器阵列; 以及提供来自选择性启用的检测器的输出的地址部分。成像阵列部分包括多个电路块，每个电路块具有主电路和冗余电路。测试电路用于提供测试信号以测试主电路中的每一个，并且确定来自测试信号的响应是否适当或不正确，并且响应于这样的确定选择信号而存储在测试电路中测试电路块。提供阵列控制器，用于在随后的正常操作模式期间向地址部分提供定时脉冲，其中地址部分根据存储的选择信号有选择地使能多个电路块中的主电路或冗余电路的检测器。

8. 发明授权

US11557235B1 Switch-based grid for resiliency and yield improvement 有权
公开(公告)号：US11557235B1
公开(公告)日：2023-01-17
申请号：US17644542
申请日：2021-12-15
申请人： Raytheon Company
发明人： Jehyuk Rhee , Bryan W. Kean , John L. Vampola
IPC分类号： G09G3/00 , G09G3/20
摘要： A device includes multiple row power lines and multiple row control lines arranged in rows, where each row control line corresponds to one of the row power lines. The device also includes multiple column power lines arranged in columns. The device further includes multiple unit cells, where each unit cell is coupled to one of the row power lines and one of the row control lines and selectively coupled to one of the column power lines. In addition, the device includes multiple row power switches and multiple column power switches arranged in pairs, where each pair includes one of the row power switches and one of the column power switches. Each pair is configured to selectively (i) connect a corresponding one of the rows and a corresponding one of the columns or (ii) isolate the corresponding one row and the corresponding one column from each other.

9. 发明申请

US20220311962A1 SINGLE-ENDED CAPACITIVE TRANS-IMPEDANCE AMPLIFIER (CTIA) UNIT CELL INCLUDING SHARED CLAMP CAPACITOR CIRCUIT FOR TWO-COLOR IMAGING 有权
公开(公告)号：US20220311962A1
公开(公告)日：2022-09-29
申请号：US17214745
申请日：2021-03-26
申请人： RAYTHEON COMPANY
发明人： Bryan W. Kean
IPC分类号： H04N5/378 , H04N5/355 , H04N5/363 , H04N9/04
摘要： A capacitive trans-impedance amplifier (CTIA) unit cell includes a CTIA and a clamp capacitor. The CTIA is configured to process a first electrical charge induced by a photocurrent. The clamp capacitor includes a first clamp terminal configured to receive a dynamic signal and a second clamp terminal connected to a CTIA output of the CTIA so as to establish an integrating node. The clamp capacitor delivers a second electrical charge to the CTIA in response to receiving the dynamic signal so as to adjust an integrating reset level at the integrating node.

10. 发明授权

US10834346B2 Programmable digital TDI EO/IR scanning focal plane array with multiple selectable TDI sub-banks 有权
公开(公告)号：US10834346B2
公开(公告)日：2020-11-10
申请号：US16426863
申请日：2019-05-30
申请人： RAYTHEON COMPANY
发明人： Steven Botts , Bryan W. Kean , Richard J. Peralta , John L. Vampola , Micky R. Harris
IPC分类号： H04N5/33 , H04N5/369 , H04N5/359 , H04N5/372 , H04N5/378
摘要： A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.

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