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1. 发明授权

US07203873B1 Asynchronous control of memory self test 有权
标题翻译：内存自检异步控制
公开(公告)号：US07203873B1
公开(公告)日：2007-04-10
申请号：US10861247
申请日：2004-06-04
申请人： R. Dean Adams , Robert Abbott , Xiaoliang Bai , Dwayne M. Burek
发明人： R. Dean Adams , Robert Abbott , Xiaoliang Bai , Dwayne M. Burek
IPC分类号： G11C29/00
CPC分类号： G11C29/14 , G11C29/1201 , G11C2029/0405
摘要： A memory logic built-in self-test (“BIST”) includes slow speed controller-to-collar signals, while allowing collars to test memories at full speed. A controller is configured to include control features and address, data, read/write, output evaluation, and redundancy calculation values are configured within the collars. The controller is further configured to handle scheduling of the collars and diagnostics interfacing. In addition, the collars are configured to allow BIST testing to be run serially, in parallel, or in groups. Collars are also configured to send diagnostic results back to the controller based on the initialization of the respective collars, thus providing a central interface for the diagnostics results.
摘要翻译：内置自检（“BIST”）的存储器逻辑包括速度较慢的控制器到外壳信号，同时允许套环全速测试存储器。控制器被配置为包括控制特征和地址，数据，读/写，输出评估和冗余计算值在套环内配置。控制器还被配置为处理套环和诊断接口的调度。此外，项圈配置为允许BIST测试串行，并行或分组运行。衣领还被配置为基于相应衣领的初始化将诊断结果发送回控制器，从而为诊断结果提供中央接口。

2. 发明授权

US5349587A Multiple clock rate test apparatus for testing digital systems 失效
标题翻译：用于测试数字系统的多时钟速率测试装置
公开(公告)号：US5349587A
公开(公告)日：1994-09-20
申请号：US858377
申请日：1992-03-26
申请人： Benoit Nadeau-Dostie , Abu S. M. Hassan , Dwayne M. Burek , Stephen K. Sunter
发明人： Benoit Nadeau-Dostie , Abu S. M. Hassan , Dwayne M. Burek , Stephen K. Sunter
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G06F11/24 , A04B17/00
CPC分类号： G01R31/31858 , G01R31/318552 , G06F11/24
摘要： In methods and apparatus for testing a digital system, scannable memory elements of the digital system are configured in a scan mode in which the memory elements are connected to define a plurality of scan chains. A test stimulus pattern is clocked into each of the scan chains at a respective clock rate, at least two of the clock rates being different from one another. The memory elements of each scan chain are then configured in a normal operation mode in which the memory elements are interconnected by the combinational network for at least one clock cycle at a highest of the respective clock rates. The memory elements are then reconfigured in the scan mode, and a test response pattern is clocked out of each of the scan chains at its respective clock rate. The methods and apparatus are particularly useful for testing digital systems such as digital integrated circuits in which different memory elements are clocked at different rates during normal operation.
摘要翻译：在用于测试数字系统的方法和装置中，数字系统的可扫描存储器元件被配置成扫描模式，其中存储器元件被连接以限定多个扫描链。以相应的时钟速率将测试刺激图案计时到每个扫描链中，至少两个时钟速率彼此不同。每个扫描链的存储器元件然后被配置为正常操作模式，其中存储器元件通过组合网络互连至少一个时钟周期，在相应时钟速率的最高处。然后在扫描模式中重新配置存储器元件，并且以各自的时钟速率从每个扫描链中计时测试响应模式。所述方法和装置对于测试诸如数字集成电路的数字系统特别有用，其中在正常操作期间不同的存储器元件以不同的速率被定时。

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