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1. 发明申请

US20060221528A1 Systems and methods for providing over-current protection in a switching power supply 有权
公开(公告)号：US20060221528A1
公开(公告)日：2006-10-05
申请号：US11396859
申请日：2006-03-31
申请人： Qiong Li , Michael Tsecouras , Dale Skelton , James Teng
发明人： Qiong Li , Michael Tsecouras , Dale Skelton , James Teng
IPC分类号： H02H3/00
CPC分类号： H02M1/32 , H02M3/156 , H05B6/06 , Y10S323/908
摘要： A system and method is provided for providing integrated over-current protection in a switching power supply. In one embodiment, a switching power supply could comprise a gate drive circuit operative to receive a pulse-width modulated (PWM) signal and to drive at least one power field effect transistor (FET) between alternating activated and deactivated states based on a pulse-width of the PWM signal. The switching power supply could also comprise a current sense circuit operative to measure a current associated with the at least one power FET during the activated state. The switching power supply could also comprise a first over-current protection circuit providing a first adjustment to the PWM signal in response to the current being substantially between a first threshold and a second threshold. The second threshold could be greater than the first threshold. The switching power supply could further comprise a second over-current protection circuit providing a second adjustment to the PWM signal in response to the current being substantially greater than the second threshold.

2. 发明授权

US06784493B2 Line self protecting multiple output power IC architecture 有权
标题翻译：线路自保护多输出电源IC架构
公开(公告)号：US06784493B2
公开(公告)日：2004-08-31
申请号：US10166956
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
IPC分类号： H01L2900
CPC分类号： H01L29/7835 , H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/1083
摘要： A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.
摘要翻译：一种功率集成电路架构（10），其具有插入在控制电路（152）和低侧晶体管（100）之间的高侧晶体管（100），以降低所述低侧晶体管对所述控制电路的操作的影响。低侧晶体管具有高p掺杂区域（56），其被设计为减少少数载流子寿命并改善少数载流子收集以减少少数载流子扰乱控制电路。低侧晶体管具有被连接到模拟地的保护（16），由此将控制电路连接到数字地，使得将少数载流子收集到模拟地中不会干扰控制电路的操作。低侧晶体管包括由至少一个深n型区域（16）分隔的多个晶体管阵列（90），该深n型区域围绕相应的晶体管阵列形成保护。防护器将一个晶体管阵列中的少数载流子与另一晶体管阵列隔离，并且便于通过其中的少数载流子的收集。

3. 发明授权

US06709900B2 Method of fabricating integrated system on a chip protection circuit 有权
标题翻译：在芯片保护电路上制造集成系统的方法
公开(公告)号：US06709900B2
公开(公告)日：2004-03-23
申请号：US10166964
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
IPC分类号： H01L21332
CPC分类号： H01L29/1083 , H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/7835
摘要： A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.
摘要翻译：一种功率集成电路架构（10），其具有插入在控制电路（152）和低侧晶体管（100）之间的高侧晶体管（100），以降低所述低侧晶体管对所述控制电路的操作的影响。低侧晶体管具有高p掺杂区域（56），其被设计为减少少数载流子寿命并改善少数载流子收集以减少少数载流子扰乱控制电路。低侧晶体管具有被连接到模拟地的保护（16），由此将控制电路连接到数字地，使得将少数载流子收集到模拟地中不会干扰控制电路的操作。低侧晶体管包括由至少一个深n型区域（16）分隔的多个晶体管阵列（90），该深n型区域围绕相应的晶体管阵列形成保护。防护器将一个晶体管阵列中的少数载流子与另一晶体管阵列隔离，并且便于通过其中的少数载流子的收集。

4. 发明授权

US06770935B2 Array of transistors with low voltage collector protection 有权
标题翻译：具有低电压采集器保护的晶体管阵列
公开(公告)号：US06770935B2
公开(公告)日：2004-08-03
申请号：US10166965
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , Dale Skelton
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , Dale Skelton
IPC分类号： H01L2701
CPC分类号： H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/1083 , H01L29/7835
摘要： An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer. The guardring is preferably grounded when utilized as the low side transistor to collect minority carriers.
摘要翻译：形成在p型层（34）中的晶体管（50）的阵列（90），并且包括在每个晶体管的漏极附近横向延伸以收集晶体管的少数载流子的第二重掺杂p型区域（56）。在p型层（34）中形成深n型区域（16）并邻近n型掩埋层（14），形成围绕多个晶体管的漏极区域的保护。晶体管阵列可以并联连接以形成大功率FET，由此重掺杂的第二p型区域（56）减少了靠近晶体管漏极的少数载流子寿命。防护（14,16）收集少数载流子（T1），并与晶体管的漏极隔离。优选地，晶体管形成在由护罩隔离的P-epi罐中。 P-epi罐优选地形成在掩埋NBL层上，并且深n型区域是延伸到掩埋NBL层的N +阱。当用作低侧晶体管以收集少数载流子时，护罩优选地接地。

5. 发明授权

US06710427B2 Distributed power device with dual function minority carrier reduction 有权
标题翻译：具有双功能少数载波减少的分布式功率器件
公开(公告)号：US06710427B2
公开(公告)日：2004-03-23
申请号：US10167136
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , David D. Briggs , Dale Skelton
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , David D. Briggs , Dale Skelton
IPC分类号： H01L2900
CPC分类号： H01L29/1083 , H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/7835
摘要： A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode (D4) between the NBL layer and the substrate will never be forward biased. In addition, each of the tank regions has a heavily doped p-type region (56) reducing the minority carrier lifetime to provide increased switching speed of the large power FET.
摘要翻译：一种分布式功率器件（100），包括通过深n型区域（16）彼此分离的多个槽区（90），并且在每个槽区中形成有多个晶体管（50）。每个槽区中的多个晶体管（50）与其它罐区中的晶体管相互连接以形成大功率FET，由此深n型区域将罐区彼此隔离。第一寄生二极管（D5）从每个槽区限定到埋层，并且在掩埋层和衬底之间限定第二寄生二极管（D4）。深n型区域相对于多个罐区域分布第一和第二寄生二极管，优选地由P-epi罐组成。深n型区域还分布形成在罐区域下方的NBL层（14）的电阻。分布式寄生二极管和NBL层的电阻有利地提供NBL层和衬底之间的寄生二极管（D4）将永远不会被正向偏置。此外，每个槽区具有重掺杂的p型区（56），减少了少量载流子寿命，以提供大功率FET的提高的开关速度。

6. 发明授权

US06175223B1 Controlled linear start-up in a linear regulator 有权
标题翻译：线性稳压器中的线性启动控制
公开(公告)号：US06175223B1
公开(公告)日：2001-01-16
申请号：US09389810
申请日：1999-09-04
申请人： Robert Martinez , Dale Skelton , David Grant
发明人： Robert Martinez , Dale Skelton , David Grant
IPC分类号： G05F140
CPC分类号： G05F1/46 , G05F1/565 , Y10S323/901
摘要： Provided is a linear voltage regulator and method of use thereof which controls the voltage input to an integrated circuit such as a digital signal processor (DSP) or a processor. The method includes the sequential steps of generating a first ramping voltage to a load connection when the load is in a start-up phase, and generating a second operating voltage to the load connection when the load is in an operational phase. The linear voltage regulator includes a control circuit and a regulation circuit that implements the method.
摘要翻译：提供一种线性电压调节器及其使用方法，其控制输入到诸如数字信号处理器（DSP）或处理器之类的集成电路的电压。该方法包括以下顺序步骤：当负载处于启动阶段时，向负载连接产生第一斜坡电压，以及当负载处于运行阶段时，向负载连接产生第二工作电压。线性稳压器包括实现该方法的控制电路和调节电路。

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