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1. 发明申请

US20070079267A1 Multi-format consistency checking tool 失效
标题翻译：多格式一致性检查工具
公开(公告)号：US20070079267A1
公开(公告)日：2007-04-05
申请号：US11242598
申请日：2005-09-30
申请人： Qiang Hong , Jing Jiang , Kevin Jones , Kathryn Mossawir , Thomas Sheffler , Paul Wong
发明人： Qiang Hong , Jing Jiang , Kevin Jones , Kathryn Mossawir , Thomas Sheffler , Paul Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule terms. In addition, certain examples allow the user to add terms to the rule set and to make new rules with the added terms. Each new term added to a rule set has a corresponding abstraction function in a translator for each design type. Thus, the abstraction functions are not design type-neutral.
摘要翻译：一种用于对具有不同设计类型的一个或多个设计表示进行一致性检查的方法和系统。每个设计类型的翻译器都可以从设计类型中立的规则中获取每个设计所需的信息。所描述的示例还允许用户使用预定义的规则术语来添加规则。此外，某些示例允许用户向规则集添加条款，并使用添加的条款创建新规则。添加到规则集中的每个新术语在每个设计类型的翻译器中都具有相应的抽象功能。因此，抽象函数不是设计类型中立的。

2. 发明申请

US20070079268A1 Mixed mode verifier 失效
标题翻译：混合模式验证器
公开(公告)号：US20070079268A1
公开(公告)日：2007-04-05
申请号：US11242599
申请日：2005-09-30
申请人： Kevin Jones , Thomas Sheffler , Kathryn Mossawir , Qiang Hong , Paul Wong , Jing Jiang
发明人： Kevin Jones , Thomas Sheffler , Kathryn Mossawir , Qiang Hong , Paul Wong , Jing Jiang
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and system for formally verifying designs having elements from more than a single design domain is described. For example, an example system allows formal verification of a design containing mixed analog and digital design.
摘要翻译：描述了用于正式验证来自多于单个设计域的元件的设计的方法和系统。例如，示例系统允许对包含混合模拟和数字设计的设计进行形式验证。

3. 发明申请

US20080263487A1 Multi-Format Consistency Checking Tool 审中-公开
标题翻译：多格式一致性检查工具
公开(公告)号：US20080263487A1
公开(公告)日：2008-10-23
申请号：US12144457
申请日：2008-06-23
申请人： Qiang Hong , JIng Jiang , Kevin D. Jones , Kathryn M. Mossawir , Thomas J. Sheffler , Paul Wong
发明人： Qiang Hong , JIng Jiang , Kevin D. Jones , Kathryn M. Mossawir , Thomas J. Sheffler , Paul Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule terms. In addition, certain examples allow the user to add terms to the rule set and to make new rules with the added terms. Each new term added to a rule set has a corresponding abstraction function in a translator for each design type. Thus, the abstraction functions are not design type-neutral.
摘要翻译：一种用于对具有不同设计类型的一个或多个设计表示进行一致性检查的方法和系统。每个设计类型的翻译器都可以从设计类型中立的规则中获取每个设计所需的信息。所描述的示例还允许用户使用预定义的规则术语来添加规则。此外，某些示例允许用户向规则集添加条款，并使用添加的条款创建新规则。添加到规则集中的每个新术语在每个设计类型的翻译器中都具有相应的抽象功能。因此，抽象函数不是设计类型中立的。

4. 发明授权

US07360187B2 Mixed mode verifier 失效
标题翻译：混合模式验证器
公开(公告)号：US07360187B2
公开(公告)日：2008-04-15
申请号：US11242599
申请日：2005-09-30
申请人： Kevin D. Jones , Thomas J. Sheffler , Kathryn M. Mossawir , Qiang Hong , Paul Wong , Jing Jiang
发明人： Kevin D. Jones , Thomas J. Sheffler , Kathryn M. Mossawir , Qiang Hong , Paul Wong , Jing Jiang
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and system for formally verifying designs having elements from more than a single design domain is described. An example system allows formal verification of a design containing mixed analog and digital subparts. The system may use different proof engines to solve an appropriate sub-partition of the entire design, and may provide a framework for translating between the different domains to create a unified result. For example, a digital proof engine may be used for a digital only subpart, while an analog proof engine may be used for an analog only subpart. The system may use the partitioning results to determine translators between the various domains, and an order in which the proof engines are applied.
摘要翻译：描述了用于正式验证来自多于单个设计域的元件的设计的方法和系统。示例系统允许对包含混合模拟和数字子部件的设计进行形式验证。系统可以使用不同的证明引擎来解决整个设计的适当子分区，并且可以提供用于在不同域之间进行翻译以创建统一结果的框架。例如，数字证明引擎可以用于仅数字的子部件，而模拟证明引擎可以用于仅模拟子部件。系统可以使用分区结果来确定各个域之间的翻译器以及应用证明引擎的顺序。

5. 发明授权

US07392492B2 Multi-format consistency checking tool 失效
标题翻译：多格式一致性检查工具
公开(公告)号：US07392492B2
公开(公告)日：2008-06-24
申请号：US11242598
申请日：2005-09-30
申请人： Qiang Hong , Jing Jiang , Kevin D. Jones , Kathryn M. Mossawir , Thomas J. Sheffler , Paul Wong
发明人： Qiang Hong , Jing Jiang , Kevin D. Jones , Kathryn M. Mossawir , Thomas J. Sheffler , Paul Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule terms. In addition, certain examples allow the user to add terms to the rule set and to make new rules with the added terms. Each new term added to a rule set has a corresponding abstraction function in a translator for each design type. Thus, the abstraction functions are not design type-neutral.
摘要翻译：一种用于对具有不同设计类型的一个或多个设计表示进行一致性检查的方法和系统。每个设计类型的翻译器都可以从设计类型中立的规则中获取每个设计所需的信息。所描述的示例还允许用户使用预定义的规则术语来添加规则。此外，某些示例允许用户向规则集添加条款，并使用添加的条款创建新规则。添加到规则集中的每个新术语在每个设计类型的翻译器中都具有相应的抽象功能。因此，抽象函数不是设计类型中立的。

6. 发明申请

US20070168172A1 Method to analyze an analog circuit design with a verification program 失效
标题翻译：用验证程序分析模拟电路设计的方法
公开(公告)号：US20070168172A1
公开(公告)日：2007-07-19
申请号：US11334063
申请日：2006-01-17
申请人： Qiang Hong , Kevin Jones , Paul Wong
发明人： Qiang Hong , Kevin Jones , Paul Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Data structures and algorithms are provided to automatically generate an analog stimulus to apply to a simulation of the analog DUT. A constraint solver is provided to determine suitable values to use in the stimulus generation. The suitable values are random values within a range of allowed values. For example, a number of different stimuli are generated for successive application to the analog DUT, each with a different magnitude within a range of allowed magnitudes. Data structures and algorithms are provided to monitor analog electrical properties at nodes of the analog DUT. Data structures and algorithms are provided to define constraints on the analog electrical properties and determine whether the constraints were violated. Data structures and algorithms are provided to define simulation coverage conditions in the analog domain and determine whether the defined analog domain coverage conditions have been satisfied.
摘要翻译：提供数据结构和算法以自动生成模拟刺激以应用于模拟DUT的仿真。提供约束求解器以确定在刺激生成中使用的合适值。合适的值是允许值范围内的随机值。例如，产生用于连续施加到模拟DUT的多个不同的刺激，每个激励在允许的幅度范围内具有不同的幅度。提供数据结构和算法来监视模拟DUT的节点处的模拟电气特性。提供数据结构和算法来定义对模拟电气特性的限制，并确定约束是否被违反。提供数据结构和算法来定义模拟域中的模拟覆盖条件，并确定是否满足了定义的模拟域覆盖条件。

7. 发明授权

US07643979B2 Method to analyze an analog circuit design with a verification program 失效
标题翻译：用验证程序分析模拟电路设计的方法
公开(公告)号：US07643979B2
公开(公告)日：2010-01-05
申请号：US11334063
申请日：2006-01-17
申请人： Qiang Hong , Kevin D. Jones , Paul Wong
发明人： Qiang Hong , Kevin D. Jones , Paul Wong
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5036
摘要： Data structures and algorithms are provided to automatically generate an analog stimulus to apply to a simulation of the analog DUT. A constraint solver is provided to determine suitable values to use in the stimulus generation. The suitable values are random values within a range of allowed values. For example, a number of different stimuli are generated for successive application to the analog DUT, each with a different magnitude within a range of allowed magnitudes. Data structures and algorithms are provided to monitor analog electrical properties at nodes of the analog DUT. Data structures and algorithms are provided to define constraints on the analog electrical properties and determine whether the constraints were violated. Data structures and algorithms are provided to define simulation coverage conditions in the analog domain and determine whether the defined analog domain coverage conditions have been satisfied.
摘要翻译：提供数据结构和算法以自动生成模拟刺激以应用于模拟DUT的仿真。提供约束求解器以确定在刺激生成中使用的合适值。合适的值是允许值范围内的随机值。例如，产生用于连续施加到模拟DUT的多个不同的刺激，每个激励在允许的幅度范围内具有不同的幅度。提供数据结构和算法来监视模拟DUT的节点处的模拟电气特性。提供数据结构和算法来定义对模拟电气特性的限制，并确定约束是否被违反。提供数据结构和算法来定义模拟域中的模拟覆盖条件，并确定是否满足了定义的模拟域覆盖条件。

8. 发明申请

US20060086403A1 Sealing device 审中-公开
标题翻译：密封装置
公开(公告)号：US20060086403A1
公开(公告)日：2006-04-27
申请号：US11241762
申请日：2005-09-29
申请人： Arne Kant , Manfred Zeuner , Rainer Samson , Paul Wong
发明人： Arne Kant , Manfred Zeuner , Rainer Samson , Paul Wong
IPC分类号： B65B31/00
CPC分类号： B60S5/04 , B29C73/166 , B29L2030/00
摘要： The present disclosure relates to a device for the sealing of inflatable objects, in particular tires, comprising a gas pressure source, a pressure hose for the connection of the gas pressure source to the inflatable object and a sealing agent contained in a removal unit. In accordance with the present disclosure, the pressure hose simultaneously forms the removal unit containing the sealing agent.
摘要翻译：本发明涉及一种用于密封可膨胀物体，特别是轮胎的装置，其包括气体压力源，用于将气体压力源连接到可膨胀物体的压力软管和包含在移除单元中的密封剂。根据本公开，压力软管同时形成包含密封剂的去除单元。

9. 发明授权

US5835502A Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme 失效
标题翻译：用于处理串行共享静态方案中可变数据字宽和阵列深度的方法和装置
公开(公告)号：US5835502A
公开(公告)日：1998-11-10
申请号：US673258
申请日：1996-06-28
申请人： Anthony Gus Aipperspach , Todd Alan Christensen , Leland Leslie Day , Paul Allen Ganfield , Murali Vaddigiri , Paul Wong
发明人： Anthony Gus Aipperspach , Todd Alan Christensen , Leland Leslie Day , Paul Allen Ganfield , Murali Vaddigiri , Paul Wong
IPC分类号： G06F12/16 , G06F11/22 , G11C29/02 , G11C29/12 , G11C29/32 , G06F11/00
CPC分类号： G11C29/32
摘要： A method and apparatus for handling variable data word widths and array depths in an array built-in self-test system for testing a plurality of memory arrays using a single controller. Each array includes a predetermined row and column address depth and data word width. Each array further includes a scan register. A universal test data word is generated and sent to the scan register of each array. The universal length test data word has a length dependent upon the maximum row address depth, maximum column address depth and/or the maximum data word width. A portion of the test data word which exceeds the column address depth, row address depth and/or the data word width of a particular array is shifted off the end of the scan register of the particular array.
摘要翻译：一种用于处理阵列内置自检系统中的可变数据字宽度和阵列深度的方法和装置，用于使用单个控制器来测试多个存储器阵列。每个阵列包括预定的行和列地址深度和数据字宽度。每个阵列还包括扫描寄存器。生成通用测试数据字并将其发送到每个阵列的扫描寄存器。通用长度测试数据字的长度取决于最大行地址深度，最大列地址深度和/或最大数据字宽度。超过特定阵列的列地址深度，行地址深度和/或数据字宽度的测试数据字的一部分从特定阵列的扫描寄存器的结尾偏移。

10. 发明申请

US20070210594A1 EGG DIPPER FOR USE IN EGG DECORATING KIT 审中-公开
标题翻译： EGG DIPPER用于EGG装饰套件
公开(公告)号：US20070210594A1
公开(公告)日：2007-09-13
申请号：US11557336
申请日：2006-11-07
申请人： Paul Wong
发明人： Paul Wong
IPC分类号： F24B15/00
CPC分类号： B44D2/002
摘要： An egg dipper for use in an egg decorating kit includes a handle and an egg holder portion pivotally attached to the handle and defining an opening for receiving at least a portion of an egg such that the egg is held by the holder portion. The handle and holder portion are formed of a plastic material and the handle pivots between an unlocked position and a locked position in which the handle is locked in place with respect to the holder portion.
摘要翻译：用于蛋装饰套件的蛋勺包括手柄和可旋转地附接到手柄的蛋保持器部分，并且限定用于容纳蛋的至少一部分的开口，使得蛋由保持器部分保持。手柄和保持器部分由塑料材料形成，并且手柄在解锁位置和锁定位置之间枢转，在该位置处手柄相对于保持器部分被锁定就位。

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