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1. 发明授权

US10523272B2 Distributed differential interconnect 有权
公开(公告)号：US10523272B2
公开(公告)日：2019-12-31
申请号：US15606820
申请日：2017-05-26
申请人： QUALCOMM Incorporated
发明人： Madhukar Vallabhaneni , Girish Koppassery , Xinhua Chen , Jingcheng Zhuang
IPC分类号： H04B3/28 , H04L25/08 , H05K1/02 , H01R9/03 , H01R9/11 , H01R11/05 , H01R12/70 , H01R12/77 , H01R12/00 , H04L25/00 , H04L25/02
摘要： An electronic apparatus is disclosed that implements a distributed differential interconnect. In an example aspect, the electronic apparatus includes a first endpoint having a first differential connection interface and a second endpoint having a second differential connection interface. The electronic apparatus also includes a differential interconnect coupled between the first differential connection interface and the second differential connection interface. The differential interconnect includes a plus pathway and a minus pathway. The plus pathway extends between the first differential connection interface and the second differential connection interface, with the plus pathway including multiple plus conductors. The minus pathway extends between the first differential connection interface and the second differential connection interface, with the minus pathway including multiple minus conductors.

2. 发明授权

US10715151B2 Fast coarse tuning for frequency synthesizer 有权
公开(公告)号：US10715151B2
公开(公告)日：2020-07-14
申请号：US15933204
申请日：2018-03-22
申请人： QUALCOMM Incorporated
发明人： Yuehai Jin , Xinhua Chen
IPC分类号： H03L7/099 , H03L7/093 , H03M3/02 , H03K5/24 , H03M1/66 , H03K5/00 , H04L7/033 , H04L5/00
摘要： A coarse tuning synthesizer for wireless communication includes a digital control unit, a digital-to-analog converter, and a comparator. The digital control unit includes an output node coupled to a first input node of a VCO (voltage controlled oscillator). The digital-to-analog converter includes a first node coupled to the first input node of the VCO. The comparator includes an output node coupled to an input node of the digital control unit. The comparator also includes a first input node coupled to a second node of the digital-to-analog converter and a second input node coupled to an output node of the VCO.

3. 发明申请

US20180343032A1 Distributed Differential Interconnect 审中-公开
公开(公告)号：US20180343032A1
公开(公告)日：2018-11-29
申请号：US15606820
申请日：2017-05-26
申请人： QUALCOMM Incorporated
发明人： Madhukar Vallabhaneni , Girish Koppassery , Xinhua Chen , Jingcheng Zhuang
IPC分类号： H04B3/28 , H04L25/02 , H04L25/08 , H05K1/02 , H01R9/03 , H01R12/00 , H01R9/11 , H01R11/05 , H01R12/70 , H01R12/77
CPC分类号： H04B3/28 , H01R9/034 , H01R9/11 , H01R11/05 , H01R12/00 , H01R12/7076 , H01R12/775 , H04L25/00 , H04L25/0274 , H04L25/085 , H05K1/0233
摘要： An electronic apparatus is disclosed that implements a distributed differential interconnect. In an example aspect, the electronic apparatus includes a first endpoint having a first differential connection interface and a second endpoint having a second differential connection interface. The electronic apparatus also includes a differential interconnect coupled between the first differential connection interface and the second differential connection interface. The differential interconnect includes a plus pathway and a minus pathway. The plus pathway extends between the first differential connection interface and the second differential connection interface, with the plus pathway including multiple plus conductors. The minus pathway extends between the first differential connection interface and the second differential connection interface, with the minus pathway including multiple minus conductors.

4. 发明授权

US09973182B2 Re-timing based clock generation and residual sideband (RSB) enhancement circuit 有权
公开(公告)号：US09973182B2
公开(公告)日：2018-05-15
申请号：US15265217
申请日：2016-09-14
申请人： QUALCOMM Incorporated
发明人： Animesh Paul , Jingcheng Zhuang , Xinhua Chen , Ravi Sridhara
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00 , H03K5/156 , H03K21/02
CPC分类号： H03K5/1565 , H03K21/02
摘要： Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.

5. 发明授权

US10177772B2 Fractional-N phase locked loop delta sigma modulator noise reduction using charge pump interpolation 有权
公开(公告)号：US10177772B2
公开(公告)日：2019-01-08
申请号：US15272307
申请日：2016-09-21
申请人： QUALCOMM Incorporated
发明人： Jingcheng Zhuang , Xinhua Chen , Frederic Bossu , Yiwu Tang
IPC分类号： H03L7/087 , H03L7/099 , H03L7/197 , H04L7/033 , H03L7/089 , H03L7/191
摘要： A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.

6. 发明授权

US09998129B1 PLL post divider phase continuity 有权
公开(公告)号：US09998129B1
公开(公告)日：2018-06-12
申请号：US15711962
申请日：2017-09-21
申请人： QUALCOMM Incorporated
发明人： Jingcheng Zhuang , Jianyun Hu , Animesh Paul , Xinhua Chen , Frederic Bossu
IPC分类号： H03D3/24 , H03L7/18 , H03L7/099 , H04L7/00 , H03L7/197 , H04L7/033 , H03L7/093
CPC分类号： H03L7/1803 , H03C3/0975 , H03L7/093 , H03L7/099 , H03L7/0992 , H03L7/18 , H03L7/197 , H03L7/1976 , H04L7/00 , H04L7/0008 , H04L7/033
摘要： A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.

7. 发明申请

US20190181844A1 LOW POWER 25% DUTY CYCLE LOCAL OSCILLATOR CLOCK GENERATION CIRCUIT 审中-公开
公开(公告)号：US20190181844A1
公开(公告)日：2019-06-13
申请号：US15835861
申请日：2017-12-08
申请人： QUALCOMM Incorporated
发明人： Animesh Paul , Xinhua Chen
IPC分类号： H03K3/017 , H03K5/02
摘要： In certain aspects, a clock generation circuit couples to a first clock having a first duty cycle and a second clock having the first duty cycle. The second clock lags the first clock by 90 degrees in phase. The clock generation circuit is configured to couple the output terminal to a ground when the first clock and the second clock both are at logic high and decouple the output terminal from the ground when at least one of the first clock and the second clock is at logic low and couple a supply voltage to the output terminal only when the first clock is at logic low and decouple the supply voltage from the output terminal when the first clock is at logic high. The clock generation circuit generates clock signals having a second duty cycle.

8. 发明申请

US20170187338A1 AMPLIFIER WITH COUPLED INDUCTORS 审中-公开
公开(公告)号：US20170187338A1
公开(公告)日：2017-06-29
申请号：US15188629
申请日：2016-06-21
申请人： QUALCOMM Incorporated
发明人： Chuan Wang , Kevin Hsi Huai Wang , Xinhua Chen , Mehmet Uzunkol
IPC分类号： H03F1/56 , H03F3/195 , H03F3/193
CPC分类号： H03F1/565 , H03F3/193 , H03F3/195 , H03F3/68 , H03F2200/111 , H03F2200/294 , H03F2200/451 , H03F2200/492
摘要： An apparatus includes an inductor device including a first inductor coupled to a second inductor. The first inductor and the second inductor are connected to ground. A first transistor and a second transistor are coupled to the inductor device. A first cascode transistor is coupled to the first transistor, and a second cascode transistor is coupled to the second transistor. The first cascode transistor is coupled to a first output, and the second cascode transistor is coupled to a second output.

9. 发明申请

US20140241335A1 PHASE-LOCKED LOOP USING DUAL LOOP MODE TO ACHIEVE FAST RESETTLING 审中-公开
标题翻译：使用双循环模式的相位锁定环来实现快速重置
公开(公告)号：US20140241335A1
公开(公告)日：2014-08-28
申请号：US13780968
申请日：2013-02-28
申请人： QUALCOMM INCORPORATED
发明人： Xinhua Chen , Yiwu Tang
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/093 , H03L7/107
摘要： A PLL operates in a first low bandwidth mode using a first control loop and in a second high bandwidth mode using a second control loop. The PLL includes a VCO that generates an output signal at a desired frequency used by a transmitter. When the transmitter switches from a High Power mode (HP TX) to a Low Power mode (LP TX), the PLL is perturbed (VCO no longer generates the desired frequency) and must resettle within an allocated time. In one example, the VCO frequency is 3.96 GHz and the settling time requirement is 25 microseconds. Upon switching from HP TX to LP TX, the PLL is switched to the second high bandwidth mode 15 microseconds and is then switched back to the first low bandwidth mode. The PLL resettles to within 1 ppm of the initial VCO frequency of 3.96 GHz within the allocated 25 microseconds.
摘要翻译： PLL使用第一控制环路在第一低带宽模式下工作，并且在第二高带宽模式中使用第二控制环路工作。 PLL包括VCO，其产生以发射机使用的期望频率的输出信号。当发射机从高功率模式（HP TX）切换到低功耗模式（LP TX）时，PLL被扰乱（VCO不再产生所需频率），并且必须在分配的时间内重新定位。在一个示例中，VCO频率为3.96GHz，建立时间要求为25微秒。从HP TX切换到LP TX时，PLL将切换到第二个高带宽模式15微秒，然后切换回第一个低带宽模式。 PLL在分配的25微秒内重置到3.96 GHz的初始VCO频率的1 ppm以内。

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