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1. 发明申请

US20180143938A1 SYSTEM AND METHOD OF SENDING DATA VIA ADDITIONAL SECONDARY DATA LINES ON A BUS 审中-公开
公开(公告)号：US20180143938A1
公开(公告)日：2018-05-24
申请号：US15875937
申请日：2018-01-19
申请人： QUALCOMM Incorporated
发明人： Gilad Sthoeger , Michael Zilbershtein , Alexander Khazin , Ben Levin
IPC分类号： G06F13/42 , G06F1/12
CPC分类号： G06F13/4282 , G06F1/12 , G06F13/423 , G06F13/4291 , Y02D10/14 , Y02D10/151
摘要： A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

2. 发明授权

US09721625B2 Time-constrained data copying between storage media 有权
公开(公告)号：US09721625B2
公开(公告)日：2017-08-01
申请号：US14722291
申请日：2015-05-27
申请人： QUALCOMM Incorporated
发明人： Lior Amarilio , Alexander Khazin
IPC分类号： G06F13/28 , G11C7/10 , G06F13/40 , G06F13/42 , G06F13/364 , G06F13/38
CPC分类号： G11C7/1075 , G06F13/287 , G06F13/364 , G06F13/385 , G06F13/4022 , G06F13/4282 , G06F13/4295 , G11C7/1036
摘要： Time-constrained data copying between storage media is disclosed. When an electronic device is engaged in real-time operations, multiple data blocks may need to be copied from one storage medium to another storage medium within certain time constraints. In this regard, a data port is operatively controlled by a plurality of registers of a first register bank. The plurality of registers is copied from the first register bank to a second register bank within a temporal limit and while the data port remains under control of the plurality of registers being copied. By copying the plurality of registers within the temporal limit, it is possible to prevent operational interruption in the data port and reduce bandwidth overhead associated with the register copying operation.

3. 发明授权

US09658645B2 Control circuits for generating output enable signals, and related systems and methods 有权
公开(公告)号：US09658645B2
公开(公告)日：2017-05-23
申请号：US14713058
申请日：2015-05-15
申请人： QUALCOMM Incorporated
发明人： Lior Amarilio , Meysam Azin , Alexander Khazin , Le Wang
IPC分类号： G06F1/00 , G06F1/10 , G06F13/42 , G06F1/06
CPC分类号： G06F1/10 , G06F1/06 , G06F13/4291
摘要： Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (SDR) data output stream. The control circuit includes a double data rate (DDR) conversion circuit configured to generate a DDR output stream based on a received SDR output stream. The control circuit includes an output enable circuit configured to receive the standard clock signal, feedback clock signal, and DDR output stream, and to generate the output enable signal that is asserted and de-asserted according to the defined timing constraints. The control circuit is configured to generate an accurately timed output enable signal without the need for a fast clock signal in addition to the standard clock signal.

4. 发明申请

US20180032307A1 POWER REDUCTION THROUGH CLOCK MANAGEMENT 有权
公开(公告)号：US20180032307A1
公开(公告)日：2018-02-01
申请号：US15725813
申请日：2017-10-05
申请人： QUALCOMM Incorporated
发明人： Alexander Khazin , Lior Amarilio
IPC分类号： G06F3/16 , G11B27/30 , H04R3/00 , G06F1/32 , G06F1/08
CPC分类号： G06F3/165 , G06F1/08 , G06F1/324 , G11B27/3036 , H04R3/00 , H04R2460/03 , Y02D10/126
摘要： Power reduction through clock management techniques are disclosed. In one aspect, the clock management is applied to a clock signal on a SOUNDWIRE™ communication bus. In particular, a control system associated with a master device on the communication bus may evaluate frequency requirements of audio streams on the communication bus and select a lowest possible clock frequency that meets the frequency requirements. Lower clock frequencies result in fewer clock transitions and result in a net power saving relative to higher clock frequencies. In the event of a clock frequency change, the master device communicates the clock frequency that will be used prospectively to slave devices on the communication bus, and all devices transition to the new frequency at the same frame boundary. In addition to the power savings, exemplary aspects of the present disclosure do not impact an active audio stream.

5. 发明申请

US20160306382A1 CONTROL CIRCUITS FOR GENERATING OUTPUT ENABLE SIGNALS, AND RELATED SYSTEMS AND METHODS 有权
标题翻译：用于产生输出使能信号的控制电路及相关系统和方法
公开(公告)号：US20160306382A1
公开(公告)日：2016-10-20
申请号：US14713058
申请日：2015-05-15
申请人： QUALCOMM Incorporated
发明人： Lior Amarilio , Meysam Azin , Alexander Khazin , Le Wang
IPC分类号： G06F1/10 , G06F1/06
CPC分类号： G06F1/10 , G06F1/06 , G06F13/4291
摘要： Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (SDR) data output stream. The control circuit includes a double data rate (DDR) conversion circuit configured to generate a DDR output stream based on a received SDR output stream. The control circuit includes an output enable circuit configured to receive the standard clock signal, feedback clock signal, and DDR output stream, and to generate the output enable signal that is asserted and de-asserted according to the defined timing constraints. The control circuit is configured to generate an accurately timed output enable signal without the need for a fast clock signal in addition to the standard clock signal.
摘要翻译：公开了用于产生输出使能信号的控制电路。在一个方面，提供了一种控制电路，其采用组合逻辑来产生使用标准时钟信号满足定时约束的输出使能信号，基于标准时钟信号的反馈时钟信号和单个数据速率（SDR）数据输出流。控制电路包括双数据速率（DDR）转换电路，配置为基于接收到的SDR输出流生成DDR输出流。控制电路包括输出使能电路，其被配置为接收标准时钟信号，反馈时钟信号和DDR输出流，并且根据定义的时序约束生成被断言和解除断言的输出使能信号。控制电路被配置为产生精确定时的输出使能信号，而不需要除了标准时钟信号之外的快速时钟信号。

6. 发明申请

US20150134862A1 SYSTEM AND METHOD OF SENDING DATA VIA ADDITIONAL SECONDARY DATA LINES ON A BUS 有权
标题翻译：通过总线上的附加二级数据线发送数据的系统和方法
公开(公告)号：US20150134862A1
公开(公告)日：2015-05-14
申请号：US14535992
申请日：2014-11-07
申请人： QUALCOMM Incorporated
发明人： Gilad Sthoeger , Michael Zilberstein , Alexander Khazin , Ben Levin
IPC分类号： G06F13/42 , G06F1/12
CPC分类号： G06F13/4282 , G06F1/12 , G06F13/423 , G06F13/4291 , Y02D10/14 , Y02D10/151
摘要： A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.
摘要翻译：串行低功率芯片间媒体总线通信链路部署在具有多个集成电路设备的设备中。可以确定耦合到通信链路的设备的通信能力，并且可以基于能力将配置或成帧消息发送到第一设备。消息可以在具有用于控制至少主数据线上的传输定时的时钟的通信链路的主数据线上发送。通信能力可以包括识别由设备支持或耦合到设备的多个数据线的信息。第一设备可以被配置为通过辅助数据线与第二设备进行通信，次级数据线可以被保留用于这种直接通信。次数据线上的通信可以使用时钟信号同步，并且可以由与用于主数据线的协议不同的协议来控制。

7. 发明授权

US10416955B2 Power reduction through clock management 有权
公开(公告)号：US10416955B2
公开(公告)日：2019-09-17
申请号：US15725813
申请日：2017-10-05
申请人： QUALCOMM Incorporated
发明人： Alexander Khazin , Lior Amarilio
IPC分类号： G06F17/00 , G06F3/16 , G06F1/08 , G06F1/324 , H04R3/00 , G11B27/30
摘要： Power reduction through clock management techniques are disclosed. In one aspect, the clock management is applied to a clock signal on a SOUNDWIRE™ communication bus. In particular, a control system associated with a master device on the communication bus may evaluate frequency requirements of audio streams on the communication bus and select a lowest possible clock frequency that meets the frequency requirements. Lower clock frequencies result in fewer clock transitions and result in a net power saving relative to higher clock frequencies. In the event of a clock frequency change, the master device communicates the clock frequency that will be used prospectively to slave devices on the communication bus, and all devices transition to the new frequency at the same frame boundary. In addition to the power savings, exemplary aspects of the present disclosure do not impact an active audio stream.

8. 发明申请

US20180225251A1 SYSTEM AND METHOD OF SENDING DATA VIA ADDITIONAL SECONDARY DATA LINES ON A BUS 审中-公开
公开(公告)号：US20180225251A1
公开(公告)日：2018-08-09
申请号：US15942277
申请日：2018-03-30
申请人： QUALCOMM Incorporated
发明人： Gilad Sthoeger , Michael Zilbershtein , Alexander Khazin , Ben Levin
IPC分类号： G06F13/42 , G06F1/12
CPC分类号： G06F13/4282 , G06F1/12 , G06F13/423 , G06F13/4291 , Y02D10/14 , Y02D10/151
摘要： A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

9. 发明申请

US20160357504A1 POWER REDUCTION THROUGH CLOCK MANAGEMENT 有权
标题翻译：通过时钟管理降低功耗
公开(公告)号：US20160357504A1
公开(公告)日：2016-12-08
申请号：US14731499
申请日：2015-06-05
申请人： QUALCOMM Incorporated
发明人： Alexander Khazin , Lior Amarilio
IPC分类号： G06F3/16 , G11B27/30
CPC分类号： G06F3/165 , G06F1/08 , G06F1/324 , G11B27/3036 , H04R3/00 , H04R2460/03 , Y02D10/126
摘要： Power reduction through clock management techniques are disclosed. In one aspect, the clock management is applied to a clock signal on a SOUNDWIRE™ communication bus. In particular, a control system associated with a master device on the communication bus may evaluate frequency requirements of audio streams on the communication bus and select a lowest possible clock frequency that meets the frequency requirements. Lower clock frequencies result in fewer clock transitions and result in a net power saving relative to higher clock frequencies. In the event of a clock frequency change, the master device communicates the clock frequency that will be used prospectively to slave devices on the communication bus, and all devices transition to the new frequency at the same frame boundary. In addition to the power savings, exemplary aspects of the present disclosure do not impact an active audio stream.
摘要翻译：通过时钟管理技术降低功耗。在一个方面，时钟管理被应用于SOUNDWIRE TM通信总线上的时钟信号。特别地，与通信总线上的主设备相关联的控制系统可以评估通信总线上的音频流的频率需求，并选择满足频率要求的最低可能时钟频率。较低的时钟频率导致更少的时钟转换，并导致相对于较高时钟频率的净功率节省。在时钟频率变化的情况下，主设备将预期使用的时钟频率传送到通信总线上的从设备，并且所有设备在相同帧边界处转换到新频率。除了功率节省之外，本公开的示例性方面不影响活动音频流。

10. 发明授权

US09229841B2 Systems and methods for detecting errors and recording actions on a bus 有权
标题翻译：用于检测总线上的错误和记录动作的系统和方法
公开(公告)号：US09229841B2
公开(公告)日：2016-01-05
申请号：US14202389
申请日：2014-03-10
申请人： QUALCOMM Incorporated
发明人： Michael Zilbershtein , Gilad Sthoeger , Alexander Khazin
IPC分类号： G06F11/00 , G06F11/34 , G06F11/30 , G06F11/22
CPC分类号： G06F11/349 , G06F11/221 , G06F11/3027
摘要： Systems and methods to detect errors and record actions on a bus are disclosed. In one embodiment, the bus is a serial low-power interchip media bus (SLIMbus) within a computing device. The SLIMbus is coupled to peripherals and a sniffer is positioned within the computing device and coupled to the SLIMbus. The sniffer mimics another SLIMbus peripheral. However, the sniffer uses a pair of multiplexers to know when to record data on the SLIMbus. The data, including the control header and payload of the data signal is captured and logged. The logged data is then exported to memory where it can be further processed so as to help debug communication on the SLIMbus.
摘要翻译：公开了在总线上检测错误和记录动作的系统和方法。在一个实施例中，总线是计算设备内的串行低功率芯片间介质总线（SLIMbus）。 SLIMbus耦合到外围设备，嗅探器位于计算设备内并与SLIMbus相连。嗅探器模仿另一个SLIMbus外设。然而，嗅探器使用一对多路复用器来知道何时在SLIMbus上记录数据。捕获并记录数据，包括数据信号的控制头和有效载荷。然后将记录的数据导出到存储器，以便进一步处理它们，以帮助调试SLIMbus上的通信。

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