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1. 发明授权

US07036067B2 Error detection for multi-stream communications 失效
标题翻译：多流通信的错误检测
公开(公告)号：US07036067B2
公开(公告)日：2006-04-25
申请号：US10402717
申请日：2003-03-28
申请人： Pulakesh Roy , Tibor Boros , Veerendra Bhora
发明人： Pulakesh Roy , Tibor Boros , Veerendra Bhora
IPC分类号： H03M13/00
CPC分类号： H04L1/0059 , H03M13/091 , H04L1/0061
摘要： According to an embodiment of the invention, a method and apparatus are described for error detection for multi-stream communication. Under an embodiment of the invention, a method for producing an error word for a data stream comprises computing an intermediate error word for each of a plurality of data sub-streams, the data stream being equivalent to a concatenation of the plurality of data sub-streams; and combining the intermediate error words to produce the error word for the data stream.
摘要翻译：根据本发明的实施例，描述了一种用于多流通信的错误检测的方法和装置。在本发明的一个实施例中，一种用于产生数据流的错误字的方法包括：计算多个数据子流中的每一个的中间错误字，该数据流等效于多个数据子流的级联，溪流并组合中间错误字以产生数据流的错误字。

2. 发明授权

US06996163B2 Walsh-Hadamard decoder 有权
标题翻译：沃尔什 - 哈达玛解码器
公开(公告)号：US06996163B2
公开(公告)日：2006-02-07
申请号：US10402039
申请日：2003-03-27
申请人： Veerendra Bhora , Pulakesh Roy , Tibor Boros
发明人： Veerendra Bhora , Pulakesh Roy , Tibor Boros
IPC分类号： H04B15/00 , H04K1/00 , H04L27/30
CPC分类号： H04B1/7093 , H04B2001/70935
摘要： In one embodiment, a Walsh-Hadamard decoder can have a hardware efficient Fast Hadamard Transform (“FHT”) engine. In one embodiment, the FHT engine can include an input to receive an input sequence to be decoded into a Walsh-Hadamard codeword. The FHT engine can further include a controller to correlate the received input sequence with a plurality of Walsh-Hadamard codewords using two add/subtract modules. In one embodiment, the two add/subtract modules operate in parallel.
摘要翻译：在一个实施例中，沃尔什 - 哈达玛解码器可以具有硬件高效的快速哈达玛变换（“FHT”）引擎。在一个实施例中，FHT引擎可以包括用于接收要解码为沃尔什 - 哈达玛码字的输入序列的输入。 FHT引擎还可以包括控制器，以使用两个加/减模块将接收的输入序列与多个沃尔什 - 哈达玛码字相关联。在一个实施例中，两个加/减模块并行操作。

3. 发明授权

US07895506B2 Iterative decoder with early-exit condition detection and methods for decoding 有权
标题翻译：具有早退条件检测的迭代解码器和解码方法
公开(公告)号：US07895506B2
公开(公告)日：2011-02-22
申请号：US11612350
申请日：2006-12-18
申请人： Veerendra Bhora , Raghavan Sudhakar
发明人： Veerendra Bhora , Raghavan Sudhakar
IPC分类号： H03M13/03
CPC分类号： H04L1/0051 , H04L1/06
摘要： Embodiments of an iterative decoder with early-exit condition detection and methods for decoding are generally described herein. Other embodiments may be described and claimed. In some embodiments, a first codeword is generated from decoded bits after one or more half-iterations of an iterative decoder, a second codeword from decoded bits after an additional half-iteration of the iterative decoder, and the first and second codewords are compared to determine whether the decoded bits are valid. In some embodiments, double or triple codeword matching is selected based on an estimated signal-to-noise ratio (SNR) and the modulation level.
摘要翻译：具有早退条件检测的迭代解码器和解码方法的实施例在此通常被描述。可以描述和要求保护其他实施例。在一些实施例中，在迭代解码器的一个或多个半迭代之后从经解码的比特生成第一码字，在迭代解码器的附加半迭代之后的解码比特中的第二码字，并将第一和第二码字与确定解码的比特是否有效。在一些实施例中，基于估计的信噪比（SNR）和调制电平来选择双码或三码字匹配。

4. 发明授权

US08068566B2 Unified multi-mode receiver detector 有权
标题翻译：统一多模接收机检测器
公开(公告)号：US08068566B2
公开(公告)日：2011-11-29
申请号：US11888228
申请日：2007-07-31
申请人： Raghavan Sudhakar , Veerendra Bhora , Kamal J. Koshy
发明人： Raghavan Sudhakar , Veerendra Bhora , Kamal J. Koshy
IPC分类号： H03D1/00
CPC分类号： H04L5/0023 , H04L1/0054 , H04L1/0631 , H04L1/0643
摘要： In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple detection modes and multiple MIMO configurations.
摘要翻译：通常，在一个方面，本公开描述了将与多输入多输出（MIMO）接收机一起使用的统一简化最大似然检测器来估计发射信号。统一检测器包括能够被用于多个检测模式和多个MIMO配置的公共框架。

5. 发明申请

US20090034662A1 Unified multi-mode receiver detector 有权
标题翻译：统一多模接收机检测器
公开(公告)号：US20090034662A1
公开(公告)日：2009-02-05
申请号：US11888228
申请日：2007-07-31
申请人： Raghavan Sudhakar , Veerendra Bhora , Kamal J. Koshy
发明人： Raghavan Sudhakar , Veerendra Bhora , Kamal J. Koshy
IPC分类号： H03D1/02
CPC分类号： H04L5/0023 , H04L1/0054 , H04L1/0631 , H04L1/0643
摘要： In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple spatial operational modes and multiple MIMO configurations.
摘要翻译：通常，在一个方面，本公开描述了将与多输入多输出（MIMO）接收机一起使用的统一简化最大似然检测器来估计发射信号。统一检测器包括能够用于多个空间操作模式和多个MIMO配置的公共框架。

6. 发明申请

US20080231479A1 Arrangements for encoding and decoding digital data 有权
标题翻译：编码和解码数字数据的安排
公开(公告)号：US20080231479A1
公开(公告)日：2008-09-25
申请号：US11725401
申请日：2007-03-19
申请人： Veerendra Bhora
发明人： Veerendra Bhora
IPC分类号： H03M7/00
CPC分类号： H03M13/4123 , H03M13/413
摘要： A method for encoding data is disclosed. The method can include receiving a first bit segment (K−1 bits) from a bit stream, storing the first bit segment, initializing an encoder with the first bit segment, start encoding and transmitting from the Kth bit to the end of the appended data stream, and appending the first bit segment (K−1 bits) to the end of the data stream. The disclose arrangements can be similar to tail-biting methods different in that the initial bits are utilized to initialize the encoded as opposed to the tail or last bit as provided by tailbiting methods.
摘要翻译：公开了一种编码数据的方法。该方法可以包括从比特流接收第一比特段（K-1比特），存储第一比特段，初始化具有第一比特段的编码器，开始编码和从第< 位到附加数据流的末尾，并将第一位段（K-1位）附加到数据流的结尾。公开的布置可以类似于尾巴方法，其不同之处在于，使用初始比特来初始化编码，而不是尾巴或最后一位，如尾巴方法所提供的。

7. 发明申请

US20080148125A1 ITERATIVE DECODER WITH EARLY-EXIT CONDITION DETECTION AND METHODS FOR DECODING 有权
标题翻译：具有早期退出条件检测的迭代解码器和解码方法
公开(公告)号：US20080148125A1
公开(公告)日：2008-06-19
申请号：US11612350
申请日：2006-12-18
申请人： Veerendra Bhora , Raghavan Sudhakar
发明人： Veerendra Bhora , Raghavan Sudhakar
IPC分类号： G06F11/10
CPC分类号： H04L1/0051 , H04L1/06
摘要： Embodiments of an iterative decoder with early-exit condition detection and methods for decoding are generally described herein. Other embodiments may be described and claimed. In some embodiments, a first codeword is generated from decoded bits after one or more half-iterations of an iterative decoder, a second codeword from decoded bits after an additional half-iteration of the iterative decoder, and the first and second codewords are compared to determine whether the decoded bits are valid. In some embodiments, double or triple codeword matching is selected based on an estimated signal-to-noise ratio (SNR) and the modulation level.
摘要翻译：具有早退条件检测的迭代解码器和解码方法的实施例在此通常被描述。可以描述和要求保护其他实施例。在一些实施例中，在迭代解码器的一个或多个半迭代之后从经解码的比特生成第一码字，在迭代解码器的附加半迭代之后的解码比特中的第二码字，并将第一和第二码字与确定解码的比特是否有效。在一些实施例中，基于估计的信噪比（SNR）和调制电平来选择双码或三码字匹配。

8. 发明授权

US07992075B2 Arrangements for encoding and decoding digital data 有权
标题翻译：编码和解码数字数据的安排
公开(公告)号：US07992075B2
公开(公告)日：2011-08-02
申请号：US11725401
申请日：2007-03-19
申请人： Veerendra Bhora
发明人： Veerendra Bhora
IPC分类号： H03M13/03
CPC分类号： H03M13/4123 , H03M13/413
摘要： A method for encoding data is disclosed. The method can include receiving a first bit segment (K−1 bits) from a bit stream, storing the first bit segment, initializing an encoder with the first bit segment, start encoding and transmitting from the Kth bit to the end of the appended data stream, and appending the first bit segment (K−1 bits) to the end of the data stream. The disclose arrangements can be similar to tail-biting methods different in that the initial bits are utilized to initialize the encoded as opposed to the tail or last bit as provided by tailbiting methods.
摘要翻译：公开了一种编码数据的方法。该方法可以包括从比特流接收第一比特段（K-1比特），存储第一比特段，初始化具有第一比特段的编码器，开始编码和从第K比特到附加数据的结尾发送流，并将第一个位段（K-1位）附加到数据流的末尾。公开的布置可以类似于尾巴方法，其不同之处在于，使用初始比特来初始化编码，而不是尾巴或最后一位，如尾巴方法所提供的。

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