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    • 5. 发明申请
    • WAFER-LEVEL TESTING METHOD FOR SINGULATED 3D-STACKED CHIP CUBES
    • 用于复合3D堆叠芯片的水平测试方法
    • US20150061718A1
    • 2015-03-05
    • US14018697
    • 2013-09-05
    • Powertech Technology Inc.
    • Kun-Chih CHANShin-Kung CHENSheng-Chi LIN
    • G01R1/073
    • G01R31/2886
    • Disclosed is a wafer level testing method for testing a plurality of singulated 3D-stacked chip cubes by utilizing adjustable wafer maps to adjust the pick-and-place positions of the cubes on a carrier wafer. The wafer maps have a plurality of probe-card activated regions each including a plurality of component-attaching regions. Two wafer-level testing steps are performed on the cubes disposed on the carrier wafer according to the wafer maps. By analyzing the electrical testing results of the trial-run wafer-level testing step from the original wafer map, some prone-to-overkill component-attaching regions are confirmed and to create a corrected wafer map which the prone-to-overkill component-attaching regions are excluded from probe-card activated regions. Then, according to the corrected wafer map, cubes are disposed on the carrier wafer without disposing in the prone-to-overkill component-attaching regions. Accordingly, the real-production wafer-level testing step can be run smoothly without unnecessary shut down of adjustment or repair leading to the maximum productivity without overkill issues.
    • 公开了一种晶片级测试方法,用于通过利用可调节的晶片图来调整载体晶片上立方体的拾取和放置位置来测试多个单独的3D堆叠芯片立方体。 晶片图具有多个探针卡激活区域,每个区域包括多个分量附着区域。 根据晶片图,在设置在载体晶片上的立方体上执行两个晶片级测试步骤。 通过从原始晶片图分析试运行晶片级测试步骤的电测试结果,确定了一些倾向于过度杀伤的部件附着区域,并且产生校正的晶片图,其中倾斜过零点成分 - 探针卡激活区域中排除附着区域。 然后,根据校正的晶片图,立方体被布置在载体晶片上,而不设置在倾斜过零点部件附着区域中。 因此,实际生产的晶片级测试步骤可以顺利地运行,而不必关闭调整或修理,导致最大的生产率而不会出现过度的问题。