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1. 发明申请

US20160181267A1 NON-VOLATILE MEMORY CELL, NAND-TYPE NON-VOLATILE MEMORY, AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：非易失性存储器单元，NAND型非易失性存储器及其制造方法
公开(公告)号：US20160181267A1
公开(公告)日：2016-06-23
申请号：US14656703
申请日：2015-03-12
申请人： Powerchip Technology Corporation
发明人： Chih-Yuan Chen , Zih-Song Wang , Hann-Ping Hwang , Tzung-Hua Ying , Yen-Cheng Fang
IPC分类号： H01L27/115 , H01L29/40 , H01L21/3065 , H01L29/49 , H01L21/308 , H01L21/306 , H01L29/66 , H01L29/423
CPC分类号： H01L21/3065 , H01L27/11524 , H01L27/11543 , H01L29/401 , H01L29/4925 , H01L29/66492 , H01L29/66553 , H01L29/66825
摘要： A non-volatile memory cell, a NAND-type non-volatile memory, and a method of manufacturing the same are provided. The method of manufacturing the non-volatile memory cell includes the following steps. An insulating layer, a first conductive layer, an inter-gate insulating layer, a second conductive layer, and a hard mask layer are formed on a substrate in order. The hard mask layer, the second conductive layer, the inter-gate insulating layer, and the first conductive layer are patterned to form a stacked gate structure. The insulating layer on the substrate at two sides of the stacked gate structure is removed until the surface of the substrate is exposed. A portion of the substrate at two sides of the stacked gate structure is removed to form two recesses in the substrate, and each of the recesses is extended below the stacked gate structure. A source/drain region is formed in the substrate below the recesses.
摘要翻译：提供了非易失性存储单元，NAND型非易失性存储器及其制造方法。制造非易失性存储单元的方法包括以下步骤。在基板上依次形成绝缘层，第一导电层，栅极间绝缘层，第二导电层和硬掩模层。将硬掩模层，第二导电层，栅极间绝缘层和第一导电层图案化以形成堆叠栅极结构。去除堆叠栅极结构两侧的衬底上的绝缘层，直到衬底的表面露出。在堆叠的栅极结构的两侧的基板的一部分被去除以在基板中形成两个凹槽，并且每个凹部在堆叠的栅极结构的下方延伸。源极/漏极区域形成在凹部下方的衬底中。

2. 发明申请

US20160172367A1 MANUFACTURING METHOD OF NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的制造方法
公开(公告)号：US20160172367A1
公开(公告)日：2016-06-16
申请号：US14601232
申请日：2015-01-21
申请人： Powerchip Technology Corporation
发明人： Kai-Yao Shih , Ssu-Ting Wang , Chi-Kai Feng , Tzung-Hua Ying , Te-Yuan Yin
IPC分类号： H01L27/115 , H01L29/66 , H01L21/311 , H01L29/40 , H01L21/265 , H01L21/266
CPC分类号： H01L27/11548 , H01L21/265 , H01L21/266 , H01L21/31111 , H01L27/11524 , H01L27/11529 , H01L27/11534 , H01L27/11543 , H01L29/401 , H01L29/6656 , H01L29/66825
摘要： A method of manufacturing a non-volatile memory is provided. A substrate including a first region and a second region is provided. A first patterning process is performed to the first region, so as to form a plurality of gate stack structures in the first region. Afterwards, a first sidewall oxide layer is formed to cover sidewalls and an upper surface of each gate stack structure, and a protection layer is then formed on the first sidewall oxide layer. Next, an ion implantation process is performed to the second region, and a second patterning process is performed to the second region so as to form a plurality of gate structures. Then, a second sidewall oxide layer covering sidewalls of each gate structure is formed.
摘要翻译：提供一种制造非易失性存储器的方法。提供了包括第一区域和第二区域的衬底。对第一区域执行第一图案化处理，以便在第一区域中形成多个栅叠层结构。然后，形成第一侧壁氧化物层以覆盖每个栅极堆叠结构的侧壁和上表面，然后在第一侧壁氧化物层上形成保护层。接下来，对第二区域进行离子注入处理，并且对第二区域进行第二图案化处理，以形成多个栅极结构。然后，形成覆盖每个栅极结构的侧壁的第二侧壁氧化物层。

3. 发明授权

US09437600B2 Flash memory structure and method of making the same 有权
标题翻译：闪存结构和制作方法相同
公开(公告)号：US09437600B2
公开(公告)日：2016-09-06
申请号：US14685614
申请日：2015-04-14
申请人： Powerchip Technology Corporation
发明人： Cheng-Yuan Hsu , Tzung-Hua Ying
IPC分类号： G11C16/10 , H01L27/115 , H01L29/788 , H01L29/66 , H01L29/423 , H01L21/3213 , H01L21/28 , G11C16/26 , G11C16/04 , G11C16/14
CPC分类号： H01L27/11521 , G11C16/0433 , G11C16/10 , G11C16/14 , G11C16/26 , H01L21/28008 , H01L21/28273 , H01L21/32133 , H01L21/32139 , H01L27/11524 , H01L29/42328 , H01L29/66825 , H01L29/788
摘要： A method of making a flash memory includes providing a substrate. Then, a first insulating layer, a first conductive layer and a second insulating layer are formed to cover the substrate. Later, a first trench is formed in the first conductive layer and the second insulating layer. After that, a second conductive layer and a mask layer are formed to cover the second insulating layer, and the second conductive layer fills up the first trench. Then, the mask layer are patterned to form patterned mask layers. Subsequently, a spacer is formed on the sidewall of the patterned mask layer. Then, an etching process is carried out by using the patterned mask layers and the spacer as a mask so as to form a first gate structure and a second gate structure.
摘要翻译：制造闪速存储器的方法包括提供衬底。然后，形成第一绝缘层，第一导电层和第二绝缘层以覆盖基板。之后，在第一导电层和第二绝缘层中形成第一沟槽。之后，形成第二导电层和掩模层以覆盖第二绝缘层，并且第二导电层填充第一沟槽。然后，对掩模层进行图案化以形成图案化掩模层。随后，在图案化掩模层的侧壁上形成间隔物。然后，通过使用图案化掩模层和间隔物作为掩模来进行蚀刻处理，以便形成第一栅极结构和第二栅极结构。

4. 发明授权

US09466605B2 Manufacturing method of non-volatile memory 有权
标题翻译：非易失性存储器的制造方法
公开(公告)号：US09466605B2
公开(公告)日：2016-10-11
申请号：US14601232
申请日：2015-01-21
申请人： Powerchip Technology Corporation
发明人： Kai-Yao Shih , Ssu-Ting Wang , Chi-Kai Feng , Tzung-Hua Ying , Te-Yuan Yin
IPC分类号： H01L21/311 , H01L21/266 , H01L27/115 , H01L21/265 , H01L29/40 , H01L29/66
CPC分类号： H01L27/11548 , H01L21/265 , H01L21/266 , H01L21/31111 , H01L27/11524 , H01L27/11529 , H01L27/11534 , H01L27/11543 , H01L29/401 , H01L29/6656 , H01L29/66825
摘要： A method of manufacturing a non-volatile memory is provided. A substrate including a first region and a second region is provided. A first patterning process is performed to the first region, so as to form a plurality of gate stack structures in the first region. Afterwards, a first sidewall oxide layer is formed to cover sidewalls and an upper surface of each gate stack structure, and a protection layer is then formed on the first sidewall oxide layer. Next, an ion implantation process is performed to the second region, and a second patterning process is performed to the second region so as to form a plurality of gate structures. Then, a second sidewall oxide layer covering sidewalls of each gate structure is formed.
摘要翻译：提供一种制造非易失性存储器的方法。提供了包括第一区域和第二区域的衬底。对第一区域执行第一图案化处理，以便在第一区域中形成多个栅叠层结构。然后，形成第一侧壁氧化物层以覆盖每个栅极堆叠结构的侧壁和上表面，然后在第一侧壁氧化物层上形成保护层。接下来，对第二区域进行离子注入处理，并且对第二区域进行第二图案化处理，以形成多个栅极结构。然后，形成覆盖每个栅极结构的侧壁的第二侧壁氧化物层。

5. 发明申请

US20160163552A1 NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20160163552A1
公开(公告)日：2016-06-09
申请号：US14621403
申请日：2015-02-13
申请人： Powerchip Technology Corporation
发明人： Cheng-Yuan Hsu , Chen-Fu Chang , Hui-Huang Chen , Tzung-Hua Ying
IPC分类号： H01L21/28 , H01L29/423 , H01L27/115
CPC分类号： H01L29/40114 , H01L27/11521 , H01L29/267 , H01L29/42328
摘要： A non-volatile memory including a substrate, a first stacked structure, a second stacked structure, a fifth conductive layer, a first doped region, and a second doped region is provided. The first stacked structure includes a first conductive layer and a second conductive layer stacked on the substrate in order and isolated from each other. The second stacked structure is separately disposed from the first stacked structure and includes a third conductive layer and a fourth conductive layer stacked on the substrate in order and connected to each other. The fifth conductive layer is disposed on the substrate at one side of the first stacked structure away from the second stacked structure. The first doped region is disposed in the substrate below the fifth conductive layer. The second doped region is disposed in the substrate at one side of the second stacked structure away from the first stacked structure.
摘要翻译：提供包括衬底，第一堆叠结构，第二堆叠结构，第五导电层，第一掺杂区和第二掺杂区的非易失性存储器。第一堆叠结构包括依次层叠在基板上的第一导电层和第二导电层，并且彼此隔离。第二层叠结构与第一层叠结构分开布置，并且包括依次并且彼此连接的层叠在基板上的第三导电层和第四导电层。第五导电层在第一堆叠结构的一侧设置在基板上，远离第二堆叠结构。第一掺杂区域设置在第五导电层下方的衬底中。所述第二掺杂区域设置在所述第二堆叠结构的离开所述第一堆叠结构的一侧的所述基板中。

6. 发明授权

US09811899B2 Method, image processing system and computer-readable recording medium for item defect inspection 有权
公开(公告)号：US09811899B2
公开(公告)日：2017-11-07
申请号：US15099609
申请日：2016-04-15
申请人： Powerchip Technology Corporation
发明人： Hao-Yu Chien , Chan-Hao Hsu , Tzung-Hua Ying
IPC分类号： G06T7/00 , G06T5/00 , G06T5/50
CPC分类号： G06T7/001 , G06T5/002 , G06T5/50 , G06T7/0008 , G06T2207/10024 , G06T2207/20021 , G06T2207/20024 , G06T2207/20072 , G06T2207/20081 , G06T2207/30148
摘要： A method, image processing system, and computer-readable recording medium for item defect inspection are provided. The method is as follows. A test image and a reference image of a test item are received. A test block and a corresponding reference block are obtained from the test image and the reference image to generate a test block image and a reference block image. The test block image and the reference block image are respectively partitioned into multiple sub-blocks. All interfering sub-blocks are identified and filtered out from the test block image and the reference block image, and a shift calibration parameter is obtained accordingly. The test block in the test image is calibrated based on the shift calibration parameter to generate a calibrated test block image. The calibrated test block image and the reference block image are compared to obtain defect information of the test item corresponding to the test block.

7. 发明申请

US20170186144A1 METHOD, IMAGE PROCESSING SYSTEM AND COMPUTER-READABLE RECORDING MEDIUM FOR ITEM DEFECT INSPECTION 有权
公开(公告)号：US20170186144A1
公开(公告)日：2017-06-29
申请号：US15099609
申请日：2016-04-15
申请人： Powerchip Technology Corporation
发明人： Hao-Yu Chien , Chan-Hao Hsu , Tzung-Hua Ying
IPC分类号： G06T7/00 , G06T5/50 , G06T5/00
CPC分类号： G06T7/001 , G06T5/002 , G06T5/50 , G06T7/0008 , G06T2207/10024 , G06T2207/20021 , G06T2207/20024 , G06T2207/20072 , G06T2207/20081 , G06T2207/30148
摘要： A method, image processing system, and computer-readable recording medium for item defect inspection are provided. The method is as follows. A test image and a reference image of a test item are received. A test block and a corresponding reference block are obtained from the test image and the reference image to generate a test block image and a reference block image. The test block image and the reference block image are respectively partitioned into multiple sub-blocks. All interfering sub-blocks are identified and filtered out from the test block image and the reference block image, and a shift calibration parameter is obtained accordingly. The test block in the test image is calibrated based on the shift calibration parameter to generate a calibrated test block image. The calibrated test block image and the reference block image are compared to obtain defect information of the test item corresponding to the test block.

8. 发明申请

US20160071854A1 FLASH MEMORY STRUCTURE AND METHOD OF MAKING THE SAME 有权
标题翻译：闪存存储器结构及其制造方法
公开(公告)号：US20160071854A1
公开(公告)日：2016-03-10
申请号：US14685614
申请日：2015-04-14
申请人： Powerchip Technology Corporation
发明人： Cheng-Yuan Hsu , Tzung-Hua Ying
IPC分类号： H01L27/115 , H01L29/66 , G11C16/26 , H01L21/3213 , H01L21/28 , G11C16/10 , H01L29/788 , H01L29/423
CPC分类号： H01L27/11521 , G11C16/0433 , G11C16/10 , G11C16/14 , G11C16/26 , H01L21/28008 , H01L21/28273 , H01L21/32133 , H01L21/32139 , H01L27/11524 , H01L29/42328 , H01L29/66825 , H01L29/788
摘要： A method of making a flash memory includes providing a substrate. Then, a first insulating layer, a first conductive layer and a second insulating layer are formed to cover the substrate. Later, a first trench is formed in the first conductive layer and the second insulating layer. After that, a second conductive layer and a mask layer are formed to cover the second insulating layer, and the second conductive layer fills up the first trench. Then, the mask layer are patterned to form patterned mask layers. Subsequently, a spacer is formed on the sidewall of the patterned mask layer. Then, an etching process is carried out by using the patterned mask layers and the spacer as a mask so as to form a first gate structure and a second gate structure.
摘要翻译：制造闪速存储器的方法包括提供衬底。然后，形成第一绝缘层，第一导电层和第二绝缘层以覆盖基板。之后，在第一导电层和第二绝缘层中形成第一沟槽。之后，形成第二导电层和掩模层以覆盖第二绝缘层，并且第二导电层填充第一沟槽。然后，对掩模层进行图案化以形成图案化掩模层。随后，在图案化掩模层的侧壁上形成间隔物。然后，通过使用图案化掩模层和间隔物作为掩模来进行蚀刻处理，以便形成第一栅极结构和第二栅极结构。

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