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1. 发明授权

US06902960B2 Oxide interface and a method for fabricating oxide thin films 有权
标题翻译：氧化物界面和氧化物薄膜的制造方法
公开(公告)号：US06902960B2
公开(公告)日：2005-06-07
申请号：US10295400
申请日：2002-11-14
申请人： Pooran Chandra Joshi , John W. Hartzell , Masahiro Adachi , Yoshi Ono
发明人： Pooran Chandra Joshi , John W. Hartzell , Masahiro Adachi , Yoshi Ono
IPC分类号： H01L21/316 , H01L21/336 , H01L29/49 , H01L29/786 , H01L21/00 , H01L21/84
CPC分类号： H01L29/66757 , H01L29/4908 , H01L29/66772
摘要： An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.
摘要翻译：提供氧化物界面和制造氧化物界面的方法。该方法包括形成硅层和覆盖硅层的氧化物层。使用电感耦合等离子体源在低于400℃的温度下形成氧化物层。在该方法的一些方面，氧化物层的厚度大于20纳米（nm），折射率在1.45和1.47之间。在该方法的一些方面，通过等离子体氧化硅层形成氧化物层，以每分钟高达约4.4nm的速率产生等离子体氧化物（1分钟后）。在该方法的某些方面，使用高密度等离子体增强化学气相沉积（HD-PECVD）工艺来形成氧化物层。在该方法的一些方面，将硅和氧化物层结合到薄膜晶体管中。

2. 发明授权

US07196383B2 Thin film oxide interface 失效
标题翻译：薄膜氧化物界面
公开(公告)号：US07196383B2
公开(公告)日：2007-03-27
申请号：US11046571
申请日：2005-01-28
申请人： Pooran Chandra Joshi , John W. Hartzell , Masahiro Adachi , Yoshi Ono
发明人： Pooran Chandra Joshi , John W. Hartzell , Masahiro Adachi , Yoshi Ono
IPC分类号： H01L29/772
CPC分类号： H01L29/66757 , H01L29/4908 , H01L29/66772
摘要： An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.
摘要翻译：提供氧化物界面和制造氧化物界面的方法。该方法包括形成硅层和覆盖硅层的氧化物层。使用电感耦合等离子体源在低于400℃的温度下形成氧化物层。在该方法的一些方面，氧化物层的厚度大于20纳米（nm），折射率在1.45和1.47之间。在该方法的一些方面，通过等离子体氧化硅层形成氧化物层，以每分钟高达约4.4nm的速率产生等离子体氧化物（1分钟后）。在该方法的某些方面，使用高密度等离子体增强化学气相沉积（HD-PECVD）工艺来形成氧化物层。在该方法的一些方面，将硅和氧化物层结合到薄膜晶体管中。

3. 发明授权

US06689646B1 Plasma method for fabricating oxide thin films 有权
标题翻译：用于制造氧化物薄膜的等离子体方法
公开(公告)号：US06689646B1
公开(公告)日：2004-02-10
申请号：US10295579
申请日：2002-11-14
申请人： Pooran Chandra Joshi , John W. Hartzell , Masahiro Adachi , Yoshi Ono
发明人： Pooran Chandra Joshi , John W. Hartzell , Masahiro Adachi , Yoshi Ono
IPC分类号： H01L2100
CPC分类号： H01L29/66757 , H01L29/78603 , H01L29/78609
摘要： A method is provided for fabricating a thin film oxide. The method include forming a first silicon layer, applying a second silicon layer overlying the first silicon layer, oxidizing the second silicon layer at a temperature of less than 400° C. using an inductively coupled plasma source, and forming a thin film oxide layer overlying the first silicon layer. In some cases, the thin film oxide layer overlies the oxidized second silicon layer and is formed by a high-density plasma enhanced chemical vapor deposition process and an inductively coupled plasma source at a temperature of less than 400° C. In some cases, the thin film oxide layer and the first silicon layer are incorporated into a thin film transistor and the thin film oxide layer has a fixed oxide charge density of 3×1011 per square centimeter.
摘要翻译：提供了制造薄膜氧化物的方法。该方法包括形成第一硅层，施加覆盖第一硅层的第二硅层，使用电感耦合等离子体源在小于400℃的温度下氧化第二硅层，以及形成覆盖层的薄膜氧化物层第一硅层。在一些情况下，薄膜氧化物层覆盖氧化的第二硅层，并且通过高密度等离子体增强化学气相沉积工艺和电感耦合等离子体源在低于400℃的温度下形成。在一些情况下，薄膜氧化物层和第一硅层结合到薄膜晶体管中，并且薄膜氧化物层具有固定的氧化物电荷密度为3×10 11每平方厘米。

4. 发明授权

US06765249B2 Thin-film transistors formed on a flexible substrate 有权
公开(公告)号：US06765249B2
公开(公告)日：2004-07-20
申请号：US10621845
申请日：2003-07-16
申请人： Apostolos T. Voutsas , John W. Hartzell , Masahiro Adachi
发明人： Apostolos T. Voutsas , John W. Hartzell , Masahiro Adachi
IPC分类号： H01L31119
CPC分类号： H01L27/1262 , G11C13/0007 , G11C2213/31 , H01L27/1214 , H01L27/1218 , H01L27/3244 , H01L27/3262 , H01L29/4908 , H01L29/66757 , H01L29/78603 , H01L51/0097 , H01L2251/5315 , H01L2251/5338 , Y02E10/549 , Y02P70/521
摘要： A method for is provided forming a thin-film transistor (TFT) on a flexible substrate. The method comprises: supplying a metal foil substrate such as titanium (Ti), Inconel alloy, stainless steel, or Kovar, having a thickness in the range of 10 to 500 microns; depositing and annealing amorphous silicon to form polycrystalline silicon; and, thermally growing a gate insulation film overlying the polycrystalline. The silicon annealing process can be conducted at a temperature greater than 700 degrees C. using a solid-phase crystallization (SPC) annealing process. Thermally growing a gate insulation film includes: forming a polycrystalline silicon layer having a thickness in the range of 10 to 100 nanometers (nm); and, thermally oxidizing the film at temperature in the range of 900 to 1150 degrees for a period of time in the range of 2 to 60 minutes. Alternately, a plasma oxide layer is deposited over a thinner thermally oxidized layer.

5. 发明授权

US06642092B1 Thin-film transistors formed on a metal foil substrate 有权
标题翻译：形成在金属箔基板上的薄膜晶体管
公开(公告)号：US06642092B1
公开(公告)日：2003-11-04
申请号：US10194895
申请日：2002-07-11
申请人： Apostolos T. Voutsas , John W. Hartzell , Masahiro Adachi
发明人： Apostolos T. Voutsas , John W. Hartzell , Masahiro Adachi
IPC分类号： H01L2100
CPC分类号： H01L27/1262 , G11C13/0007 , G11C2213/31 , H01L27/1214 , H01L27/1218 , H01L27/3244 , H01L27/3262 , H01L29/4908 , H01L29/66757 , H01L29/78603 , H01L51/0097 , H01L2251/5315 , H01L2251/5338 , Y02E10/549 , Y02P70/521
摘要： A method for is provided forming a thin-film transistor (TFT) on a flexible substrate. The method comprises: supplying a metal foil substrate such as titanium (Ti), Inconel alloy, stainless steel, or Kovar, having a thickness in the range of 10 to 500 microns; depositing and annealing amorphous silicon to form polycrystalline silicon; and, thermally growing a gate insulation film overlying the polycrystalline. The silicon annealing process can be conducted at a temperature greater than 700 degrees C. using a solid-phase crystallization (SPC) annealing process. Thermally growing a gate insulation film includes: forming a polycrystalline silicon layer having a thickness in the range of 10 to 100 nanometers (nm); and, thermally oxidizing the film at temperature in the range of 900 to 1150 degrees for a period of time in the range of 2 to 60 minutes. Alternately, a plasma oxide layer is deposited over a thinner thermally oxidized layer.
摘要翻译：提供一种在柔性基板上形成薄膜晶体管（TFT）的方法。该方法包括：提供具有10至500微米厚度的金属箔基底如钛（Ti），铬镍铁合金，不锈钢或科瓦尔; 沉积和退火非晶硅以形成多晶硅; 并且热堆积覆盖多晶的栅极绝缘膜。硅退火工艺可以使用固相结晶（SPC）退火工艺在大于700℃的温度下进行。制造栅极绝缘膜的方法包括：形成厚度为10〜100纳米（nm）的多晶硅层; 并将膜的温度在900〜1150度的范围内热氧化2〜60分钟的时间。或者，等离子体氧化物层沉积在较薄的热氧化层上。

6. 发明申请

US20050136695A1 Thin film oxide interface 失效
标题翻译：薄膜氧化物界面
公开(公告)号：US20050136695A1
公开(公告)日：2005-06-23
申请号：US11046571
申请日：2005-01-28
申请人： Pooran Joshi , John Hartzell , Masahiro Adachi , Yoshi Ono
发明人： Pooran Joshi , John Hartzell , Masahiro Adachi , Yoshi Ono
IPC分类号： H01L21/316 , H01L21/336 , H01L29/49 , H01L29/786 , H01L23/58 , H01L21/26 , H01L21/324 , H01L21/42 , H01L21/477
CPC分类号： H01L29/66757 , H01L29/4908 , H01L29/66772
摘要： An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.
摘要翻译：提供氧化物界面和制造氧化物界面的方法。该方法包括形成硅层和覆盖硅层的氧化物层。使用电感耦合等离子体源在低于400℃的温度下形成氧化物层。在该方法的一些方面，氧化物层的厚度大于20纳米（nm），折射率在1.45和1.47之间。在该方法的一些方面，通过等离子体氧化硅层形成氧化物层，以每分钟高达约4.4nm的速率产生等离子体氧化物（1分钟后）。在该方法的某些方面，使用高密度等离子体增强化学气相沉积（HD-PECVD）工艺来形成氧化物层。在该方法的一些方面，将硅和氧化物层结合到薄膜晶体管中。

7. 发明授权

US08927962B2 Group III nitride semiconductor optical device 有权
标题翻译： III族氮化物半导体光学器件
公开(公告)号：US08927962B2
公开(公告)日：2015-01-06
申请号：US13055690
申请日：2010-02-26
申请人： Masaki Ueno , Yusuke Yoshizumi , Yohei Enya , Takashi Kyono , Katsushi Akita , Takamichi Sumitomo , Masahiro Adachi , Shinji Tokuyama
发明人： Masaki Ueno , Yusuke Yoshizumi , Yohei Enya , Takashi Kyono , Katsushi Akita , Takamichi Sumitomo , Masahiro Adachi , Shinji Tokuyama
IPC分类号： H01L29/66 , H01L33/32 , H01S5/343 , B82Y20/00 , H01L33/16 , H01S5/32
CPC分类号： H01S5/34333 , B82Y20/00 , H01L33/16 , H01L33/32 , H01L33/325 , H01S5/3202
摘要： A group III nitride semiconductor optical device 11a has a group III nitride semiconductor substrate 13 having a main surface 13a forming a finite angle with a reference plane Sc orthogonal to a reference axis Cx extending in a c-axis direction of the group III nitride semiconductor and an active layer 17 of a quantum-well structure, disposed on the main surface 13a of the group III nitride semiconductor substrate 13, including a well layer 28 made of a group III nitride semiconductor and a plurality of barrier layers 29 made of a group III nitride semiconductor. The main surface 13a exhibits semipolarity. The active layer 17 has an oxygen content of at least 1×1017 cm−3 but not exceeding 8×1017 cm−3. The plurality of barrier layers 29 contain an n-type impurity other than oxygen by at least 1×1017 cm−3 but not exceeding 1×1019 cm−3 in an upper near-interface area 29u in contact with a lower interface 28Sd of the well layer 28 on the group III nitride semiconductor substrate side.
摘要翻译： III族氮化物半导体光学元件11a具有III族氮化物半导体衬底13，该III族氮化物半导体衬底13具有与在III族氮化物半导体的c轴方向上延伸的参考轴Cx正交的参考平面Sc形成有限角度的主表面13a; 设置在III族氮化物半导体衬底13的主表面13a上的量子阱结构的有源层17，包括由III族氮化物半导体制成的阱层28和由III族组成的多个势垒层29 氮化物半导体。主表面13a具有半极性。活性层17的氧含量至少为1×1017cm-3，但不超过8×1017cm-3。多个势垒层29在上接近界面区域29u中含有除氧之外的至少1×1017cm-3但不超过1×1019cm-3的n型杂质，该上接近界面区29u与下界面28Sd接触 III族氮化物半导体衬底侧的阱层28。

8. 发明申请

US20110291673A1 CHEMICAL SENSOR 审中-公开
标题翻译：化学传感器
公开(公告)号：US20110291673A1
公开(公告)日：2011-12-01
申请号：US13147798
申请日：2010-02-08
申请人： Yoshinori Shibata , Masahiro Adachi
发明人： Yoshinori Shibata , Masahiro Adachi
IPC分类号： G01R27/28 , H01L29/66
CPC分类号： G01N27/4145 , G01N27/4148
摘要： Provided is a chemical sensor requiring no ion-sensitive film. Specifically provided is a chemical sensor (1) for detecting a sample base material (19) to be detected in a sample, the chemical sensor (1) including: a sensor TFT (7) of sensor TFTs (7) each of which has a glass substrate (8) and, on the glass substrate (8), a gate electrode (10), a gate oxide film (11), a silicon layer (12), a source electrode (14), and a drain electrode (15), the silicon layer (12) having a channel region (18) at an opening portion between the source electrode (14) and the drain electrode (15); and extracting signal lines PAS1 to PASn and a sensor signal amplifying and extracting circuit (24) that extract a leak current that is generated in the channel region (18).
摘要翻译：提供了不需要离子敏感膜的化学传感器。具体地提供一种用于检测样品中要检测的样品基材（19）的化学传感器（1），所述化学传感器（1）包括：传感器TFT（7）的传感器TFT（7），每个传感器TFT具有玻璃基板（8），并且在玻璃基板（8）上具有栅电极（10），栅极氧化膜（11），硅层（12），源电极（14）和漏电极（15）），所述硅层（12）在所述源电极（14）和所述漏电极（15）之间的开口部分具有沟道区（18）; 以及提取信号线PAS1〜PASn和提取在通道区域（18）中产生的泄漏电流的传感器信号放大和提取电路（24）。

9. 发明申请

US20110221707A1 DISPLAY DEVICE HAVING OPTICAL SENSOR 审中-公开
标题翻译：具有光学传感器的显示设备
公开(公告)号：US20110221707A1
公开(公告)日：2011-09-15
申请号：US13129103
申请日：2009-06-25
申请人： Kei Oyobe , Masahiro Adachi
发明人： Kei Oyobe , Masahiro Adachi
IPC分类号： G06F3/042
CPC分类号： G06F3/0412 , G02F1/13338 , G06F3/042 , G09G3/3648 , G09G2354/00 , G09G2360/147
摘要： A plurality of pixel circuits are provided on a TFT-side substrate 11, light blocking layers 15 and light blocking layer openings 16 are provided between the pixel circuits, and optical sensors 17 are arranged at positions where the light blocking layers 15 are provided. Light blocking layers 18 are also provided at opposing portions of the opposite substrate 12, and light reflecting units 19 are provided correspondingly to the optical sensors 17. In the normal state, backlight BL that has passed through the TFT-side substrate 11 is reflected by the light reflecting unit 19 and falls on the optical sensor 17. When the front surface of the liquid crystal panel is pressed, the two substrates come close to each other, the light reflection direction in the light reflecting unit 19 changes, and the intensity of light detected by the optical sensor 17 changes. By subjecting the obtained sensor image to an image recognition process, it is possible to eliminate the effect of the external light and detect the touch position on the display screen with high accuracy.
摘要翻译：在TFT侧基板11上设置多个像素电路，在像素电路之间设置有遮光层15和遮光层开口16，并且在设置有遮光层15的位置配置有光学传感器17。遮光层18也设置在相对基板12的相对部分处，并且光反射单元19对应于光学传感器17设置。在正常状态下，已经通过TFT侧基板11的背光BL被光反射单元19落在光学传感器17上。当按压液晶面板的前表面时，两个基板彼此靠近，光反射单元19中的光反射方向变化，并且强度由光学传感器17检测到的光改变。通过对获得的传感器图像进行图像识别处理，可以消除外部光的影响并且以高精度检测显示屏上的触摸位置。

10. 发明授权

US07960918B2 Electronic device and light emission control method for electronic device 有权
标题翻译：电子设备的电子设备和发光控制方法
公开(公告)号：US07960918B2
公开(公告)日：2011-06-14
申请号：US11992592
申请日：2008-02-04
申请人： Masahiro Adachi , Yutaka Hashimoto , Katsuhisa Kanzaki , Tomoki Abe , Hirofumi Kasada , Koshi Ando
发明人： Masahiro Adachi , Yutaka Hashimoto , Katsuhisa Kanzaki , Tomoki Abe , Hirofumi Kasada , Koshi Ando
IPC分类号： H05B41/30
CPC分类号： H05B33/0848 , H05B33/089
摘要： An electronic device, and a corresponding light emission control method for the electronic device, emit light by utilizing recombination of electrons and holes the device and method input a pulse-shaped driving signal having a duty ratio higher than or equal to 0.7 and lower than 1.0 and thereby causing light to be emitted intermittently. When an electron density is denoted by n, a hole density by p, a thermal velocity of electrons by Vth:n, a thermal velocity of holes by Vth:p, an electron capture cross section of a defect level by σn, a hole capture cross section of a defect level by σp, and a pulse width of the driving signal by W, the input driving signal has a pulse width W that satisfies W
摘要翻译：电子设备和相应的电子设备的发光控制方法通过利用电子和空穴的复合来发光，该装置和方法输入占空比高于或等于0.7且低于1.0的脉冲驱动信号从而间歇地发光。当电子密度由n表示时，空穴密度为p，电子的热速度为Vth：n，空穴的热速度为Vth：p，缺陷水平的电子捕获截面为＆sgr; n，a 缺陷电平的孔捕获截面为＆sgr; p，驱动信号的脉冲宽度为W，输入驱动信号的脉冲宽度W满足W <1 / {n·vth：n·＆sgr; n· p·vth：p·＆sgr; p /（n·vth：n·＆sgr; n + p·vth：p·＆sgr; p）}。

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