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1. 发明申请

US20120313178A1 SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有金属门的半导体器件及其制造方法
公开(公告)号：US20120313178A1
公开(公告)日：2012-12-13
申请号：US13158479
申请日：2011-06-13
申请人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yeng-Peng Wang , Chun-Hsien Lin , Chan-Lon Yang , Guang-Yaw Hwang , Shin-Chi Chen , Hung-Ling Shih , Jiunn-Hsiung Liao , Chia-Wen Liang
发明人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yeng-Peng Wang , Chun-Hsien Lin , Chan-Lon Yang , Guang-Yaw Hwang , Shin-Chi Chen , Hung-Ling Shih , Jiunn-Hsiung Liao , Chia-Wen Liang
IPC分类号： H01L21/3205 , H01L29/78
CPC分类号： H01L29/78 , H01L21/823842 , H01L21/82385 , H01L29/66545
摘要： A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.
摘要翻译：一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层，在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层栅极沟槽，以及去除牺牲掩模层。第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。第一导电类型和第二导电类型是互补的。

2. 发明授权

US08704294B2 Semiconductor device having metal gate and manufacturing method thereof 有权
标题翻译：具有金属栅极的半导体器件及其制造方法
公开(公告)号：US08704294B2
公开(公告)日：2014-04-22
申请号：US13158479
申请日：2011-06-13
申请人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yeng-Peng Wang , Chun-Hsien Lin , Chan-Lon Yang , Guang-Yaw Hwang , Shin-Chi Chen , Hung-Ling Shih , Jiunn-Hsiung Liao , Chia-Wen Liang
发明人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yeng-Peng Wang , Chun-Hsien Lin , Chan-Lon Yang , Guang-Yaw Hwang , Shin-Chi Chen , Hung-Ling Shih , Jiunn-Hsiung Liao , Chia-Wen Liang
IPC分类号： H01L29/66
CPC分类号： H01L29/78 , H01L21/823842 , H01L21/82385 , H01L29/66545
摘要： A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.
摘要翻译：一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层，在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层栅极沟槽，以及去除牺牲掩模层。第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。第一导电类型和第二导电类型是互补的。

3. 发明授权

US09384962B2 Oxygen treatment of replacement work-function metals in CMOS transistor gates 有权
标题翻译： CMOS晶体管栅极中替代工作功能金属的氧化处理
公开(公告)号：US09384962B2
公开(公告)日：2016-07-05
申请号：US13082387
申请日：2011-04-07
申请人： Guang-Yaw Hwang , Chun-Hsien Lin , Hung-Ling Shih , Jiunn-Hsiung Liao , Zhi-Cheng Lee , Shao-Hua Hsu , Yi-Wen Chen , Cheng-Guo Chen , Jung-Tsung Tseng , Chien-Ting Lin , Tong-Jyun Huang , Jie-Ning Yang , Tsung-Lung Tsai , Po-Jui Liao , Chien-Ming Lai , Ying-Tsung Chen , Cheng-Yu Ma , Wen-Han Hung , Che-Hua Hsu
发明人： Guang-Yaw Hwang , Chun-Hsien Lin , Hung-Ling Shih , Jiunn-Hsiung Liao , Zhi-Cheng Lee , Shao-Hua Hsu , Yi-Wen Chen , Cheng-Guo Chen , Jung-Tsung Tseng , Chien-Ting Lin , Tong-Jyun Huang , Jie-Ning Yang , Tsung-Lung Tsai , Po-Jui Liao , Chien-Ming Lai , Ying-Tsung Chen , Cheng-Yu Ma , Wen-Han Hung , Che-Hua Hsu
IPC分类号： H01L21/28 , H01L21/02
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7845 , H01L29/7846
摘要： A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.
摘要翻译：提供一种制造金属栅极的方法。该方法包括提供基板。然后，在基板上形成栅极电介质层。在栅极电介质层上形成具有功函数金属层的多层堆叠结构。在多层堆叠结构的至少一层上进行O2气氛处理。在多层堆叠结构上形成导电层。

4. 发明申请

US20120256276A1 Metal Gate and Fabricating Method Thereof 有权
标题翻译：金属门及其制造方法
公开(公告)号：US20120256276A1
公开(公告)日：2012-10-11
申请号：US13082387
申请日：2011-04-07
申请人： Guang-Yaw Hwang , Chun-Hsien Lin , Hung-Ling Shih , Jiunn-Hsiung Liao , Zhi-Cheng Lee , Shao-Hua Hsu , Yi-Wen Chen , Cheng-Guo Chen , Jung-Tsung Tseng , Chien-Ting Lin , Tong-Jyun Huang , Jie-Ning Yang , Tsung-Lung Tsai , Po-Jui Liao , Chien-Ming Lai , Ying-Tsung Chen , Cheng-Yu Ma , Wen-Han Hung , Che-Hua Hsu
发明人： Guang-Yaw Hwang , Chun-Hsien Lin , Hung-Ling Shih , Jiunn-Hsiung Liao , Zhi-Cheng Lee , Shao-Hua Hsu , Yi-Wen Chen , Cheng-Guo Chen , Jung-Tsung Tseng , Chien-Ting Lin , Tong-Jyun Huang , Jie-Ning Yang , Tsung-Lung Tsai , Po-Jui Liao , Chien-Ming Lai , Ying-Tsung Chen , Cheng-Yu Ma , Wen-Han Hung , Che-Hua Hsu
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7845 , H01L29/7846
摘要： A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.
摘要翻译：提供一种制造金属栅极的方法。该方法包括提供基板。然后，在基板上形成栅极电介质层。在栅极电介质层上形成具有功函数金属层的多层堆叠结构。在多层堆叠结构的至少一层上进行O2气氛处理。在多层堆叠结构上形成导电层。

5. 发明申请

US20120244669A1 Method of Manufacturing Semiconductor Device Having Metal Gates 有权
标题翻译：制造具有金属门的半导体器件的方法
公开(公告)号：US20120244669A1
公开(公告)日：2012-09-27
申请号：US13053223
申请日：2011-03-22
申请人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yi-Wei Chen , Hsin-Fu Huang , Tzung-Ying Lee , Min-Chuan Tsai , Chan-Lon Yang , Chun-Yuan Wu , Teng-Chun Tsai , Guang-Yaw Hwang , Chia-Lin Hsu , Jie-Ning Yang , Cheng-Guo Chen , Jung-Tsung Tseng , Zhi-Cheng Lee , Hung-Ling Shih , Po-Cheng Huang , Yi-Wen Chen , Che-Hua Hsu
发明人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yi-Wei Chen , Hsin-Fu Huang , Tzung-Ying Lee , Min-Chuan Tsai , Chan-Lon Yang , Chun-Yuan Wu , Teng-Chun Tsai , Guang-Yaw Hwang , Chia-Lin Hsu , Jie-Ning Yang , Cheng-Guo Chen , Jung-Tsung Tseng , Zhi-Cheng Lee , Hung-Ling Shih , Po-Cheng Huang , Yi-Wen Chen , Che-Hua Hsu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.
摘要翻译：本发明提供一种制造具有金属栅极的半导体器件的方法。首先，提供基板。具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。去除第一牺牲栅极以形成第一沟槽。然后，在第一沟槽中形成第一金属层。去除第二牺牲栅极以形成第二沟槽。接下来，在第一沟槽和第二沟槽中形成第二金属层。最后，在第二金属层上形成第三金属层，其中第三金属层被填充到第一沟槽和第二沟槽中。

6. 发明授权

US08802524B2 Method of manufacturing semiconductor device having metal gates 有权
标题翻译：制造具有金属栅极的半导体器件的方法
公开(公告)号：US08802524B2
公开(公告)日：2014-08-12
申请号：US13053223
申请日：2011-03-22
申请人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yi-Wei Chen , Hsin-Fu Huang , Tzung-Ying Lee , Min-Chuan Tsai , Chan-Lon Yang , Chun-Yuan Wu , Teng-Chun Tsai , Guang-Yaw Hwang , Chia-Lin Hsu , Jie-Ning Yang , Cheng-Guo Chen , Jung-Tsung Tseng , Zhi-Cheng Lee , Hung-Ling Shih , Po-Cheng Huang , Yi-Wen Chen , Che-Hua Hsu
发明人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yi-Wei Chen , Hsin-Fu Huang , Tzung-Ying Lee , Min-Chuan Tsai , Chan-Lon Yang , Chun-Yuan Wu , Teng-Chun Tsai , Guang-Yaw Hwang , Chia-Lin Hsu , Jie-Ning Yang , Cheng-Guo Chen , Jung-Tsung Tseng , Zhi-Cheng Lee , Hung-Ling Shih , Po-Cheng Huang , Yi-Wen Chen , Che-Hua Hsu
IPC分类号： H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/823807 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.
摘要翻译：本发明提供一种制造具有金属栅极的半导体器件的方法。首先，提供基板。具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。去除第一牺牲栅极以形成第一沟槽。然后，在第一沟槽中形成第一金属层。去除第二牺牲栅极以形成第二沟槽。接下来，在第一沟槽和第二沟槽中形成第二金属层。最后，在第二金属层上形成第三金属层，其中第三金属层被填充到第一沟槽和第二沟槽中。

7. 发明授权

US08298935B2 Dual damascene process 有权
标题翻译：双镶嵌工艺
公开(公告)号：US08298935B2
公开(公告)日：2012-10-30
申请号：US12952179
申请日：2010-11-22
申请人： Shin-Chi Chen , Yu-Tsung Lai , Jiunn-Hsiung Liao , Guang-Yaw Hwang
发明人： Shin-Chi Chen , Yu-Tsung Lai , Jiunn-Hsiung Liao , Guang-Yaw Hwang
IPC分类号： H01L21/4763
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76811
摘要： A dual damascene process is disclosed. The process includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the dielectric layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask, wherein the second aperture and the first aperture comprise a gap therebetween; and utilizing the second patterned mask as etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
摘要翻译：公开了一种双镶嵌工艺。该方法包括以下步骤：在基底上形成电介质层; 在所述电介质层上形成第一图案化掩模，其中所述第一图案化掩模包括开口; 在所述电介质层上形成材料层并覆盖所述第一图案化掩模; 在所述电介质层上形成第二图案化掩模，其中所述第二图案化掩模包括第一孔; 在所述第二图案化掩模中形成第二孔，其中所述第二孔和所述第一孔包括它们之间的间隙; 并且利用第二图案化掩模作为蚀刻掩模，用于通过第一孔和第二孔部分去除材料层和介电层。

8. 发明授权

US08791013B2 Pattern forming method 有权
标题翻译：图案形成方法
公开(公告)号：US08791013B2
公开(公告)日：2014-07-29
申请号：US13568137
申请日：2012-08-07
申请人： Shin-Chi Chen , Yu-Tsung Lai , Jiunn-Hsiung Liao , Guang-Yaw Hwang
发明人： Shin-Chi Chen , Yu-Tsung Lai , Jiunn-Hsiung Liao , Guang-Yaw Hwang
IPC分类号： H01L21/4763
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76811
摘要： A pattern forming method is disclosed. The method includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the material layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask after forming the first aperture, wherein the second aperture and the first aperture comprise a gap therebetween and overlap the opening; and utilizing the second patterned mask as an etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
摘要翻译：公开了图案形成方法。该方法包括以下步骤：在基底上形成电介质层; 在所述电介质层上形成第一图案化掩模，其中所述第一图案化掩模包括开口; 在所述电介质层上形成材料层并覆盖所述第一图案化掩模; 在所述材料层上形成第二图案化掩模，其中所述第二图案化掩模包括第一孔; 在形成所述第一孔之后在所述第二图案化掩模中形成第二孔，其中所述第二孔和所述第一孔包括它们之间的间隙并与所述开口重叠; 并且利用第二图案化掩模作为蚀刻掩模，用于通过第一孔和第二孔部分去除材料层和介电层。

9. 发明申请

US20120129337A1 DUAL DAMASCENE PROCESS 有权
标题翻译：双重加工过程
公开(公告)号：US20120129337A1
公开(公告)日：2012-05-24
申请号：US12952179
申请日：2010-11-22
申请人： Shin-Chi Chen , Yu-Tsung Lai , Jiunn-Hsiung Liao , Guang-Yaw Hwang
发明人： Shin-Chi Chen , Yu-Tsung Lai , Jiunn-Hsiung Liao , Guang-Yaw Hwang
IPC分类号： H01L21/768
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76811
摘要： A dual damascene process is disclosed. The process includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the dielectric layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask, wherein the second aperture and the first aperture comprise a gap therebetween; and utilizing the second patterned mask as etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.
摘要翻译：公开了一种双镶嵌工艺。该方法包括以下步骤：在基底上形成电介质层; 在所述电介质层上形成第一图案化掩模，其中所述第一图案化掩模包括开口; 在所述电介质层上形成材料层并覆盖所述第一图案化掩模; 在所述电介质层上形成第二图案化掩模，其中所述第二图案化掩模包括第一孔; 在所述第二图案化掩模中形成第二孔，其中所述第二孔和所述第一孔包括它们之间的间隙; 并且利用第二图案化掩模作为蚀刻掩模，用于通过第一孔和第二孔部分去除材料层和介电层。

10. 发明授权

US08552503B2 Strained silicon structure 有权
标题翻译：应变硅结构
公开(公告)号：US08552503B2
公开(公告)日：2013-10-08
申请号：US12957304
申请日：2010-11-30
申请人： Guang-Yaw Hwang , Ling-Chun Chou , I-Chang Wang , Shin-Chuan Huang , Jiunn-Hsiung Liao , Shin-Chi Chen , Pau-Chung Lin , Chiu-Hsien Yeh , Chin-Cheng Chien , Chieh-Te Chen
发明人： Guang-Yaw Hwang , Ling-Chun Chou , I-Chang Wang , Shin-Chuan Huang , Jiunn-Hsiung Liao , Shin-Chi Chen , Pau-Chung Lin , Chiu-Hsien Yeh , Chin-Cheng Chien , Chieh-Te Chen
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/088 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.
摘要翻译：应变硅衬底结构包括设置在衬底上的第一晶体管和第二晶体管。第一晶体管包括第一栅极结构和设置在第一栅极结构的两侧的两个第一源极/漏极区域。第一源极/漏极到栅极间距在每个第一源极/漏极区域和第一栅极结构之间。第二晶体管包括第二栅极结构和设置在第二栅极结构的两侧的两个源极/漏极掺杂区域。第二源极/漏极到栅极间距在每个第二源极/漏极区域和第二栅极结构之间。第一源极/漏极到栅极距离小于第二源极/漏极到栅极距离。

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