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1. 发明授权

US08467294B2 Dynamic load balancing for port groups 有权
标题翻译：端口组的动态负载均衡
公开(公告)号：US08467294B2
公开(公告)日：2013-06-18
申请号：US12931821
申请日：2011-02-11
申请人： Pirabhu Raman , Deepak Cherian , Hariharan Balasubramanian , Ramprasad Nagaraja Rao
发明人： Pirabhu Raman , Deepak Cherian , Hariharan Balasubramanian , Ramprasad Nagaraja Rao
IPC分类号： G01R31/08
CPC分类号： H04L47/125 , H04L47/30
摘要： In one embodiment, a method includes receiving a packet at an input port of a network device, the input port having a plurality of queues with at least one queue for each output port at the network device, identifying a port group for transmitting the packet from the network device, the port group having a plurality of members each associated with one of the output ports, and selecting one of the queues based on utilization of the members. An apparatus for load balancing is also disclosed.
摘要翻译：在一个实施例中，一种方法包括在网络设备的输入端口处接收分组，所述输入端口具有多个队列，其具有用于网络设备处的每个输出端口的至少一个队列，标识用于从所述网络设备发送分组的端口组所述网络设备，所述端口组具有多个成员，每个成员与所述输出端口之一相关联，并且基于所述成员的使用来选择所述队列之一。还公开了一种用于负载平衡的装置。

2. 发明申请

US20120207175A1 Dynamic load balancing for port groups 有权
标题翻译：端口组的动态负载均衡
公开(公告)号：US20120207175A1
公开(公告)日：2012-08-16
申请号：US12931821
申请日：2011-02-11
申请人： Pirabhu Raman , Deepak Cherian , Hariharan Balasubramanian , Ramprasad Nagaraja Rao
发明人： Pirabhu Raman , Deepak Cherian , Hariharan Balasubramanian , Ramprasad Nagaraja Rao
IPC分类号： H04L12/56
CPC分类号： H04L47/125 , H04L47/30
摘要： In one embodiment, a method includes receiving a packet at an input port of a network device, the input port having a plurality of queues with at least one queue for each output port at the network device, identifying a port group for transmitting the packet from the network device, the port group having a plurality of members each associated with one of the output ports, and selecting one of the queues based on utilization of the members. An apparatus for load balancing is also disclosed.
摘要翻译：在一个实施例中，一种方法包括在网络设备的输入端口处接收分组，所述输入端口具有多个队列，其具有用于网络设备处的每个输出端口的至少一个队列，标识用于从所述网络设备发送分组的端口组所述网络设备，所述端口组具有多个成员，每个成员与所述输出端口之一相关联，并且基于所述成员的使用来选择所述队列之一。还公开了一种用于负载平衡的装置。

3. 发明授权

US08909860B2 Executing parallel operations to increase data access performance 有权
标题翻译：执行并行操作以增加数据访问性能
公开(公告)号：US08909860B2
公开(公告)日：2014-12-09
申请号：US13592793
申请日：2012-08-23
申请人： Ramprasad Nagaraja Rao
发明人： Ramprasad Nagaraja Rao
IPC分类号： G06F13/00
CPC分类号： G06F11/1012
摘要： Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read or write access is increased by partitioning a memory into a group of sub-blocks, associating a parity block with the sub-blocks, and accessing the sub-blocks to read data as needed. Write access is increased by including a latency cache that stores data associated with a read command. Once a read-modify write command is received, the data stored in the data cache is used to update the parity block. In a memory without a parity block, write access is increased by adding one or more spare memory blocks to provide additional memory locations for performing write operations to the same memory block in parallel.
摘要翻译：描述了用于增加存储器设备的数据访问性能的技术。在各种实施例中，调度器/控制器被配置为在从存储器读取或从存储器写入时管理数据。通过将存储器划分成一组子块，将奇偶校验块与子块相关联，以及根据需要访问子块以读取数据来增加读取或写入访问。通过包括存储与读取命令相关联的数据的延迟高速缓存来增加写入访问。一旦读取 - 修改写入命令被接收，存储在数据高速缓存中的数据被用于更新奇偶校验块。在没有奇偶校验块的存储器中，通过添加一个或多个备用存储器块来提供写访问以提供用于并行地对相同存储器块执行写操作的附加存储器位置。

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