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1. 发明授权

US07130589B2 Self-calibrating apparatus and method in a mobile transceiver 有权
标题翻译：移动收发器中的自校准装置和方法
公开(公告)号：US07130589B2
公开(公告)日：2006-10-31
申请号：US10815445
申请日：2004-04-01
申请人： Kwy-Ro Lee , Pil-Soon Choi , Mi-Hyun Son , Seong-Soo Lee
发明人： Kwy-Ro Lee , Pil-Soon Choi , Mi-Hyun Son , Seong-Soo Lee
IPC分类号： H04B17/00 , H03C1/62 , H04Q7/20
CPC分类号： H04L27/364 , H04B17/0085 , H04B17/21 , H04L2027/0016 , H04L2027/0018 , H04L2027/0026
摘要： An apparatus and method for self-calibrating mismatching orthogonal signals and non-linearity of a circuit occurring in a mobile transceiver. For this, in a mobile terminal, a transmitter is used as a signal generator and a receiver is used as a response characteristic measurer. A base band processor calibrates mismatching signals and non-linearity in a reception side and a transmission side, based on a test signal received via the transmitter and a test signal received via the receiver.
摘要翻译：用于自校准错配正交信号和在移动收发机中发生的电路的非线性的装置和方法。为此，在移动终端中，使用发射机作为信号发生器，并且使用接收机作为响应特性测量器。基带处理器基于经由发送器接收的测试信号和经由接收器接收的测试信号来校准接收侧和发送侧的不匹配信号和非线性。

2. 发明授权

US07103332B2 Apparatus and method for compensating for frequency offset in a mobile communication system 有权
标题翻译：用于补偿移动通信系统中的频率偏移的装置和方法
公开(公告)号：US07103332B2
公开(公告)日：2006-09-05
申请号：US10799034
申请日：2004-03-12
申请人： Pil-Soon Choi , Mi-Hyun Son , Seong-Soo Lee , Kwy-Ro Lee
发明人： Pil-Soon Choi , Mi-Hyun Son , Seong-Soo Lee , Kwy-Ro Lee
IPC分类号： H04B1/18 , H04B17/00
CPC分类号： H03D3/007 , H04L27/22 , H04L2027/0024 , H04L2027/0046 , H04L2027/0065
摘要： An apparatus and method for compensating for the frequency offset of a received signal in a receiving apparatus of a mobile communication system. In the present invention, a sine component is calculated by adding I and Q channel signals resulting from downconverting a training sequence inserted between data symbols, and a cosine component is calculated by subtracting the Q channel signal from the I channel signal. Using the cosine and sine components at two time points, tangent components for the two time points are computed and thus first and second phase values are obtained. The frequency offset is estimated by determining the slope of a second-order line derived from the first and second phase values. The frequency offset of the received signal is compensated for based on the estimated frequency offset.
摘要翻译：一种用于补偿移动通信系统的接收装置中的接收信号的频率偏移的装置和方法。在本发明中，通过将插入在数据符号之间的训练序列下变频得到的I和Q信道信号相加，计算出正弦分量，并且通过从I信道信号中减去Q信道信号来计算余弦分量。在两个时间点使用余弦和正弦分量，计算两个时间点的切线分量，从而获得第一和第二相位值。通过确定从第一和第二相位值导出的二阶线的斜率来估计频率偏移。基于估计的频率偏移来补偿接收信号的频率偏移。

3. 发明授权

US06614328B2 Radio frequency filter of combline structure having frequency cut-off circuit and method for implementing the same 失效
公开(公告)号：US06614328B2
公开(公告)日：2003-09-02
申请号：US10080512
申请日：2002-02-25
申请人： Mi-Hyun Son , Seong-Soo Lee
发明人： Mi-Hyun Son , Seong-Soo Lee
IPC分类号： H01P120
CPC分类号： H01P1/20336
摘要： Disclosed is a radio frequency filter of a combline structure including a frequency cut-off circuit for cutting off a specific frequency from a frequency band having a given frequency bandwidth. The frequency cut-off circuit includes an inductive transmission line extending from the output terminal by a length determined to provide an approximate inductance corresponding to a calculated value approximate to an inductance for obtaining the specific frequency, and a capacitive element coupled to the approximate inductance provided by the inductive transmission line, so that it has a capacitance for obtaining the specific frequency. The inductive transmission line is connected to the capacitive element through a via hole formed at an end of the transmission line opposite to the output terminal, from which the transmission line extends. The invention also proposes a method for implementing the radio frequency filter.

4. 发明申请

US20060170503A1 Small-sized on-chip CMOS power amplifier having improved efficiency 有权
标题翻译：具有提高效率的小尺寸片上CMOS功率放大器
公开(公告)号：US20060170503A1
公开(公告)日：2006-08-03
申请号：US11323744
申请日：2005-12-30
申请人： Jae-Sup Lee , Hyun-Il Kang , Seong-Soo Lee , Holger Lothar , Ju-Hyun Ko , Dong-Hyun Baek , Song-Cheol Hong
发明人： Jae-Sup Lee , Hyun-Il Kang , Seong-Soo Lee , Holger Lothar , Ju-Hyun Ko , Dong-Hyun Baek , Song-Cheol Hong
IPC分类号： H03F3/14
CPC分类号： H03F3/604 , H03F1/02 , H03F1/22 , H03F3/195 , H03F3/265 , H03F2200/537 , H03F2200/541
摘要： A small-sized on-chip complementary metal-oxide semiconductor (CMOS) Power Amplifier having improved efficiency is provided herein. The on-chip CMOS power amplifier is capable of improving efficiency and maximizing output thereof by enhancing a K factor, which may cause a problem in a power amplifier having a distributed active transformer structure. The on-chip CMOS power amplifier having an improved efficiency and being fabricated in a small size, the on-chip CMOS power amplifier includes a primary winding located at a first layer, secondary windings located at a second layer, which is an upper part of the first layer, the secondary windings being located corresponding to a position of the primary winding, and a cross section for coupling the second windings with each other.
摘要翻译：本文提供了具有提高的效率的小尺寸片上互补金属氧化物半导体（CMOS）功率放大器。片上CMOS功率放大器能够通过增强K因子来提高效率并使其输出最大化，这可能导致具有分布式有源变压器结构的功率放大器的问题。片上CMOS功率放大器具有改进的效率并以小尺寸制造，片上CMOS功率放大器包括位于第一层的初级绕组，位于第二层的次级绕组，其位于第二层的上部第一层，次级绕组对应于初级绕组的位置，以及用于将第二绕组彼此联接的横截面。

5. 发明授权

US07379844B2 Particle sampling method and sensor fusion and filtering method 有权
标题翻译：粒子采样方法和传感器融合与滤波方法
公开(公告)号：US07379844B2
公开(公告)日：2008-05-27
申请号：US11276127
申请日：2006-02-15
申请人： Suk-Han Lee , Seong-Soo Lee , Jang-Yong Lee , Seung-Min Baek
发明人： Suk-Han Lee , Seong-Soo Lee , Jang-Yong Lee , Seung-Min Baek
IPC分类号： G06F15/00 , G06F7/60
CPC分类号： G05B13/04 , G05B17/02
摘要： Disclosed is a technique for obtaining an estimate and variance of each variable based on a constraint manifold. Particles (or samples) are sampled in order to filter and fuse ambiguous data or information on at least one state variable of a system using the particles. The sampling is carried out in consideration of an influence which non-linearity of the constraint manifold of a system model, an observation model or another system model exerts on a probability distribution of the state variable. With this construction, it is possible to reduce decrease of fusion and filtering performance, decrease a Gaussian approximation error, and detect mismatched information.
摘要翻译：公开了一种基于约束歧管获得每个变量的估计和方差的技术。对粒子（或样本）进行采样，以便使用粒子对系统的至少一个状态变量进行过滤和融合不明确的数据或信息。考虑到系统模型，观测模型或其他系统模型的约束歧管的非线性对状态变量的概率分布施加的影响来进行抽样。利用这种结构，可以减少融合和滤波性能的降低，降低高斯近似误差，并检测不匹配的信息。

6. 发明申请

US20050245225A1 Wideband I/Q signal generation device 有权
标题翻译：宽带I / Q信号发生装置
公开(公告)号：US20050245225A1
公开(公告)日：2005-11-03
申请号：US11089219
申请日：2005-03-24
申请人： Yun-Seo Park , Sang-Hyun Woo , Hwan-Seok Song , Seong-Soo Lee , Chang-Ho Lee , Joy Laskar
发明人： Yun-Seo Park , Sang-Hyun Woo , Hwan-Seok Song , Seong-Soo Lee , Chang-Ho Lee , Joy Laskar
IPC分类号： H04B1/40 , H03D7/16 , H03H7/20 , H03H7/21 , H04B1/16 , H04B1/26 , H04B15/00
CPC分类号： H03D7/165 , H03H7/20 , H03H7/21 , H03H2007/0192
摘要： An apparatus for generating an in-phase/quadrature-phase (I/Q) signal in a wireless transceiver is disclosed, including a local oscillator for generating a local oscillation signal, and first and second mixers for mixing the oscillation signal with a transmission/reception signal to convert the transmission/reception signal into a baseband or high-frequency signal. The apparatus includes a phase locked circuit for controlling the local oscillator, and a polyphase filter installed between the local oscillator and the mixers, for separating the oscillation signal from the local oscillator into an I signal and a Q signal depending on a control signal from the phase locked circuit, and outputting the separated I and Q signals to the first and second mixers, respectively.
摘要翻译：公开了一种用于在无线收发机中产生同相/正交相（I / Q）信号的装置，包括用于产生本地振荡信号的本地振荡器，以及用于将振荡信号与发送/ 接收信号将发送/接收信号转换为基带或高频信号。该装置包括用于控制本地振荡器的锁相电路和安装在本地振荡器和混频器之间的多相滤波器，用于根据来自该振荡器的控制信号将振荡信号与本地振荡器分离成I信号和Q信号并且将分离的I和Q信号分别输出到第一和第二混频器。

7. 发明申请

US20050225371A1 Impulse generation circuit 失效
标题翻译：脉冲发生电路
公开(公告)号：US20050225371A1
公开(公告)日：2005-10-13
申请号：US11082537
申请日：2005-03-17
申请人： Young-Hwan Kim , Seong-Soo Lee , Hak-Sun Kim , Chang-Seok Lee , Soo-Yong Park , Yu-Sin Kim
发明人： Young-Hwan Kim , Seong-Soo Lee , Hak-Sun Kim , Chang-Seok Lee , Soo-Yong Park , Yu-Sin Kim
IPC分类号： H03K3/017 , A61N1/18 , H03K5/06
CPC分类号： H03K5/06
摘要： An impulse generation circuit is provided for generating an impulse using a transmission line. Impulse characteristics of the impulse generation circuit are varied with the length of a transmission line rather than the characteristic variation of various devices used therein. The length of the transmission line is adjusted, such that a width of a generated pulse is adjusted. Because an end of the transmission line is short-circuited, the transmission line length can be easily adjusted on a substrate, and a ringing phenomenon due to re-reflection can be removed using termination impedance.
摘要翻译：提供脉冲发生电路，用于使用传输线产生脉冲。脉冲发生电路的脉冲特性随着传输线的长度而不同于其中使用的各种装置的特性变化而变化。调整传输线的长度，使得产生的脉冲的宽度被调整。由于传输线的一端短路，因此可以在基板上容易地调整传输线路长度，并且可以使用终端阻抗来消除由于再反射引起的振铃现象。

8. 发明授权

US08557661B2 Methods of manufacturing a semiconductor device and a semiconductor memory device thereby 有权
标题翻译：因此制造半导体器件和半导体存储器件的方法
公开(公告)号：US08557661B2
公开(公告)日：2013-10-15
申请号：US13314627
申请日：2011-12-08
申请人： Han-Geun Yu , Gyung-Jin Min , Seong-Soo Lee , Suk-Ho Joo , Yoo-Chul Kong , Dae-Hyun Jang
发明人： Han-Geun Yu , Gyung-Jin Min , Seong-Soo Lee , Suk-Ho Joo , Yoo-Chul Kong , Dae-Hyun Jang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/11565 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L27/11575 , H01L27/11582
摘要： A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.
摘要翻译：一种制造半导体器件的方法包括在存储单元区域上形成存储单元，在连接区域上交替地形成牺牲层和绝缘中间层，以提供配置为电连接存储单元的布线，形成包括蚀刻掩模图案在顶部牺牲层上的元件，在每个蚀刻掩模图案元件的每个侧壁上形成阻挡侧壁，形成第一光致抗蚀剂图案，选择性地将第一阻挡侧壁从存储器单元区域最远地覆盖并覆盖其它阻挡侧壁，蚀刻暴露顶部牺牲层和绝缘中间层以暴露第二牺牲层，通过横向去除第一光致抗蚀剂图案至第二阻挡侧壁暴露的程度形成第二光致抗蚀剂图案，并将暴露的顶部和第二牺牲层和绝缘夹层蚀刻到形成一个楼梯形状 d侧边缘部分。

9. 发明授权

US07348676B2 Semiconductor device having a metal wiring structure 有权
标题翻译：具有金属布线结构的半导体器件
公开(公告)号：US07348676B2
公开(公告)日：2008-03-25
申请号：US11149600
申请日：2005-06-09
申请人： Seong-Soo Lee
发明人： Seong-Soo Lee
IPC分类号： H01L23/48
CPC分类号： H01L21/76877 , H01L21/76802 , H01L21/76838 , H01L21/76843 , H01L21/76847 , H01L21/76883 , H01L23/485 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： After an insulation layer is formed on a substrate, a contact hole is formed through the insulation layer. A recessed plug is formed to partially fill up the contact hole. The recessed plug has a height substantially smaller than a depth of the contact hole. A metal wiring structure is formed on the recessed plug and on the insulation layer. A lower portion of the metal wiring structure, formed within the contact hole, prevents damage to the recessed plug during an etching process for forming the metal wiring structure. Therefore, the recessed plug may be formed without damage thereof even if an alignment error occurs between an etching mask and the recessed plug during metal wiring structure formation.
摘要翻译：在基板上形成绝缘层之后，通过绝缘层形成接触孔。形成一个凹形插头以部分地填充接触孔。凹形插塞的高度显着小于接触孔的深度。金属布线结构形成在凹形插塞和绝缘层上。形成在接触孔内的金属布线结构的下部防止了在用于形成金属布线结构的蚀刻工艺期间对凹形插塞的损坏。因此，即使在金属布线结构形成期间在蚀刻掩模和凹入插塞之间发生定向误差，也可以形成凹形插塞而不损坏凹形插塞。

10. 发明授权

US07253707B2 Tunable active inductor 有权
标题翻译：可调谐有源电感
公开(公告)号：US07253707B2
公开(公告)日：2007-08-07
申请号：US11141123
申请日：2005-05-31
申请人： Rajarshi Mukhopadhy , Sebastien Nuttinck , Sang-Hyun Woo , Jong-Han Kim , Seong-Soo Lee , Chang-Ho Lee , Joy Laskar
发明人： Rajarshi Mukhopadhy , Sebastien Nuttinck , Sang-Hyun Woo , Jong-Han Kim , Seong-Soo Lee , Chang-Ho Lee , Joy Laskar
IPC分类号： H03H11/00 , H03H11/04
CPC分类号： H03H11/50 , H03H11/48
摘要： An active inductor capable of tuning a self-resonant frequency, an inductance, a Q factor, and a peak Q frequency by applying a tunable feedback resistor to a cascode-grounded active inductor is disclosed. The tunable active inductor includes a first transistor having a source connected to a power supply voltage and a gate connected to first bias voltage; a second transistor having a drain connected to a drain of the first transistor and a gate connected to a second bias voltage; a third transistor having a drain connected to a source of the second transistor and a source connected to a ground voltage; a fourth transistor having a drain connected to a gate of the third transistor, a source connected to the ground voltage and a gate connected to a third bias voltage; a fifth transistor having a source connected to the drain of the fourth transistor and a drain connected to the power supply voltage.
摘要翻译：公开了一种通过将可调谐反馈电阻器施加到共源共栅接地有源电感器来调谐自谐振频率，电感，Q因子和峰值Q频率的有源电感器。可调谐有源电感器包括具有连接到电源电压的源极和连接到第一偏置电压的栅极的第一晶体管; 第二晶体管，具有连接到所述第一晶体管的漏极的漏极和连接到第二偏置电压的栅极; 具有连接到所述第二晶体管的源极的漏极和连接到接地电压的源极的第三晶体管; 具有连接到第三晶体管的栅极的漏极的第四晶体管，连接到接地电压的源极和连接到第三偏置电压的栅极; 第五晶体管，其源极连接到第四晶体管的漏极，漏极连接到电源电压。

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