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1. 发明申请

US20080267260A1 DYMANIC INTERPOLATION LOCATION 有权
标题翻译： DYMANIC插值位置
公开(公告)号：US20080267260A1
公开(公告)日：2008-10-30
申请号：US11931906
申请日：2007-10-31
申请人： Pierre BERTRAND , David J. HOYLE , Eric BISCONDI
发明人： Pierre BERTRAND , David J. HOYLE , Eric BISCONDI
IPC分类号： H04B1/707
CPC分类号： H04B1/707
摘要： Apparatus and method for optimizing interpolation in the despreader data-path of a wireless telecommunications network employing CDMA technology. A base station dynamically evaluates its configuration to determine an interpolator location. The location of the interpolator in a despreader data-path is dynamically selected. A received signal is interpolated. The despread received signals are combined, and further processing is applied to the combined signal. To enhance system performance, the interpolator may be located at least to perform chip-sample interpolation per antenna stream at chip rate, chip-sample interpolation per user at chip rate, or symbol-sample interpolation per user at (sub) symbol rate.
摘要翻译：在采用CDMA技术的无线电信网络的解扩器数据路径中优化内插的装置和方法。基站动态地评估其配置以确定内插器位置。动态地选择内插器在解扩器数据路径中的位置。接收到的信号被内插。解扩后的接收信号进行组合，对组合信号进行进一步处理。为了提高系统性能，内插器可以至少位于以码片速率每芯片速率的每个天线流进行芯片样本插值，以码片速率对每个用户进行芯片样本插值，或以（子）符号率对每个用户进行符号样本插值。

2. 发明申请

US20100169735A1 LOW DENSITY PARITY CHECK CODE ROW UPDATE INSTRUCTION 审中-公开
标题翻译：低密度奇偶校验检查代码更新指令
公开(公告)号：US20100169735A1
公开(公告)日：2010-07-01
申请号：US12347731
申请日：2008-12-31
申请人： Eric BISCONDI , David J. HOYLE , Tod D. WOLF
发明人： Eric BISCONDI , David J. HOYLE , Tod D. WOLF
IPC分类号： H03M13/05 , G06F11/07
CPC分类号： H03M13/1117 , H03M13/6502 , H03M13/6544
摘要： Apparatus for optimizing low-density parity check (“LDPC”) decoding in a processor is disclosed herein. A processor in accordance with the present disclosure includes an LDPC decoder row update execution unit. The LDPC decoder row update execution unit accelerates an LDPC row update computation by performing a logarithm estimation and a magnitude minimization in parallel. The execution unit is activated by execution of an LDPC row update instruction. The execution unit adds a minimum of magnitudes of two input values to a difference of estimated logarithms of exponential functions of a sum and a difference of the two input values to produce a row update value.
摘要翻译：本文公开了一种在处理器中优化低密度奇偶校验（“LDPC”）解码的装置。根据本公开的处理器包括LDPC解码器行更新执行单元。 LDPC解码器行更新执行单元通过并行执行对数估计和幅度最小化来加速LDPC行更新计算。通过执行LDPC行更新指令来激活执行单元。执行单元将两个输入值的最小量值添加到两个输入值的和的指数函数的估计对数与差的估计对数之间的差，以产生行更新值。

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