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1. 发明授权

US4970641A Exception handling in a pipelined microprocessor 失效
标题翻译：流水线微处理器中的异常处理
公开(公告)号：US4970641A
公开(公告)日：1990-11-13
申请号：US344429
申请日：1989-04-26
申请人： Phillip D. Hester , William A. Johnson
发明人： Phillip D. Hester , William A. Johnson
IPC分类号： G06F11/00 , G06F12/10 , G11C29/00
CPC分类号： G11C29/88 , G06F12/10 , G06F11/076
摘要： A method for processing address translation exceptions occurring in a virtual memory system employing demand paging and having a plurality of registers and a real storage area, includes the steps of: (a) temporarily storing for each storage operation; (i) the effective storage address for the operation; (ii) exception control word information relative to the ones of the registers involved in the operation and the length and type of the operation; and (iii) any data to be stored during the operation; (b) retrieving the temporarily stored information to form an exception status block if an exception is generated indicating a failed operation; and (c) reinitiating the failed operation based on the information contained in the exception status block.
摘要翻译：一种用于处理在采用需求寻呼并具有多个寄存器和实际存储区域的虚拟存储器系统中发生的地址转换异常的方法包括以下步骤：（a）为每个存储操作临时存储; （i）操作的有效存储地址; （ii）相对于操作中涉及的寄存器的异常控制字信息以及操作的长度和类型; 和（iii）在操作期间要存储的任何数据; （b）如果产生指示故障操作的异常，则检索临时存储的信息以形成异常状态块; （c）根据异常状态块中包含的信息重新启动失败的操作。

2. 发明授权

US4788683A Data processing system emulation with microprocessor in place 失效
标题翻译：数据处理系统仿真与微处理器就位
公开(公告)号：US4788683A
公开(公告)日：1988-11-29
申请号：US143308
申请日：1988-01-07
申请人： Phillip D. Hester , William M. Johnson
发明人： Phillip D. Hester , William M. Johnson
IPC分类号： G01R31/3185 , G06F11/26 , G06F11/273 , G06F11/30
CPC分类号： G06F11/261 , G01R31/318505 , G01R31/318572 , G06F11/2733
摘要： Apparatus is provided for testing a data processing system which includes a microprocessor, the testing occurring with the microprocessor in place in the system. The apparatus comprises: a support microprocessor for controlling the testing, a serial-to-parallel and parallel-to-serial converter connected between the support microprocessor and the system microprocessor, means for supplying a series of level sensitive scan design (LSSD) test signals from the support microprocessor through the converter to the system microprocessor, and means for returning the results of the level sensitive scan design test signals from the system microprocessor through the converter to the support microprocessor.
摘要翻译：提供了用于测试包括微处理器的数据处理系统的装置，该微处理器在系统中就位的测试发生。该装置包括：用于控制测试的支持微处理器，连接在支持微处理器和系统微处理器之间的串并行和并 - 串转换器，用于提供一系列电平敏感扫描设计（LSSD）测试信号的装置从支持微处理器通过转换器到系统微处理器，以及用于将来自系统微处理器的电平敏感扫描设计测试信号的结果通过转换器返回到支持微处理器的装置。

3. 发明授权

US5146570A System executing branch-with-execute instruction resulting in next successive instruction being execute while specified target instruction is prefetched for following execution 失效
标题翻译：执行执行分支执行指令的系统，导致下一个连续指令在指定的目标指令被预取以执行以后执行
公开(公告)号：US5146570A
公开(公告)日：1992-09-08
申请号：US547423
申请日：1990-07-03
申请人： Phillip D. Hester , William M. Johnson
发明人： Phillip D. Hester , William M. Johnson
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3842
摘要： A method and apparatus are described for expanding the capability of an instruction prefetch buffer. The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required. However, if the two values of the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required. The method and apparatus are also applicable to the use of branch-with-execute instructions wherein a subject instruction is executed immediately following the branch-with-execute instruction. The execution of this subject instruction before the branch target instruction enables the system processor to continue operating while it is waiting for the branch target instruction.
摘要翻译：描述了用于扩展指令预取缓冲器的能力的方法和装置。该方法和装置使得指令预取缓冲器能够区分在指令流中的分支之前发生的旧预取和在指令流中的分支之后发生的新的预取。每当将指令的请求发送到存储器时，就产生一个控制标签。返回指令附加了原始控制标签，然后将其与指令预取缓冲器中的控制标签的当前值进行比较。如果两个值相匹配，则表示分支未发生，仍然需要指令。但是，如果控制标签的两个值不相等，则表示指令流中的分支已经发生，并且不再需要从存储器发送到缓冲区的指令。该方法和装置也适用于使用分支执行指令，其中在分支执行指令之后立即执行主题指令。在分支目标指令之前执行该主题指令使系统处理器在等待分支目标指令时继续运行。

4. 发明授权

US4775927A Processor including fetch operation for branch instruction with control tag 失效
标题翻译：处理器包括带控制标签的分支指令的提取操作
公开(公告)号：US4775927A
公开(公告)日：1988-10-04
申请号：US666790
申请日：1984-10-31
申请人： Phillip D. Hester , William M. Johnson
发明人： Phillip D. Hester , William M. Johnson
IPC分类号： G06F9/32 , G06F9/38 , G06F12/02
CPC分类号： G06F9/3804 , G06F9/3842 , G06F9/3889
摘要： A method and apparatus expands the capability of an instruction prefetch buffer. The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required. However, if the two values of the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required. The method and apparatus are also applicable to the use of branch-with-execute instructions wherein a subject instruction is executed immediately following the branch-with-execute instruction. The execution of this subject instruction before the branch target instruction enables the system processor to continue operating while it is waiting for the branch target instruction.

5. 再颁专利

USRE34052E Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage 失效
公开(公告)号：USRE34052E
公开(公告)日：1992-09-01
申请号：US285827
申请日：1988-12-16
申请人： Phillip D. Hester , William M. Johnson
发明人： Phillip D. Hester , William M. Johnson
IPC分类号： G06F9/315 , G06F15/78
CPC分类号： G06F9/30032 , G06F15/7832
摘要： The present invention is directed to a conventional data processing system having a CPU and at least one external unit such as the main storage unit acquiring data from or providing data to the CPU and I/O bus for the transfer of data between the CPU and the external unit. The apparatus of the present invention provides for transfers to and from this external unit, e.g., main storage being overlapped with a register to register data transfer routinely carried out in the CPU to implement various CPU operations and computation functions. The CPU includes apparatus for transferring data to or from said external unit over the I/O bus during synchronized time cycles. The CPU also includes local storage apparatus which comprise a plurality of registers as well as expedients for transferring data from register to register. Control apparatus controls the register to register data transfer so that such transfers are conducted during time cycles coincident with the transfer of data to or from the external storage unit. Thus, the register to register data transfers within the CPU are overlapped with the data transfers over the I/O bus to main storage. The data transfers to and from main storage are generally considerably longer than the simpler register to register data transfer. The apparatus may be operated so that several register to register transfers may take place during the time required for a transfer of data to or from the external storage unit. The present invention further includes means for dynamically determining data dependencies between the register to register transfers and the I/O bus transfers.

6. 发明授权

US4680700A Virtual memory address translation mechanism with combined hash address table and inverted page table 失效
标题翻译：具有组合哈希地址表和反转页表的虚拟内存地址转换机制
公开(公告)号：US4680700A
公开(公告)日：1987-07-14
申请号：US845228
申请日：1986-12-19
申请人： Phillip D. Hester , Richard O. Simpson
发明人： Phillip D. Hester , Richard O. Simpson
IPC分类号： G06F12/10 , G06F13/00 , G06F9/36
CPC分类号： G06F12/1036 , G06F12/1018 , G06F2212/652
摘要： A virtual memory address translation mechanism is provided for converting virtual memory addresses provided by a CPU into real memory addresses within page frames in a large hierachial memory wherein the real memory space is substantially smaller than the scope of the virtual memory. The conversion or translation mechanism includes a combined table in the memory which includes a first list covering the respective virtual address of each memory address (Inverted Page Table or IPT) and a second list connecting each of a plurality of hashed addresses with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address (Hashed Addressed Table, HAT). The system also has means for hashing a selected virtual address to produce a hashed address. Also included is apparatus for sequentially searching through the linked group of virtual addresses in the combined table until a selected virtual address is located as well as apparatus responsive to the location of a particular selected virtual address for accessing from the first list, the real memory address of the located virtual address.
摘要翻译：提供了一种虚拟存储器地址转换机制，用于将由CPU提供的虚拟存储器地址转换成大型层级存储器中的页内的实际存储器地址，其中实际存储器空间实质上小于虚拟存储器的范围。转换或转换机制包括存储器中的组合表，其包括覆盖每个存储器地址（反向页表或IPT）的相应虚拟地址的第一列表和连接多个散列地址中的每一个与预定初始虚拟链接的虚拟地址组的地址，当散列产生连接的散列地址（Hash Adressed Table，HAT）时，每个虚拟地址的地址。该系统还具有用于散列选择的虚拟地址以产生散列地址的装置。还包括用于在组合表中顺序地搜索所链接的虚拟地址组的设备，直到所选择的虚拟地址被定位，以及响应于特定所选择的虚拟地址的位置以响应于从第一列表访问的设备，实际存储器地址的位置的虚拟地址。

7. 发明授权

US4630195A Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage 失效
标题翻译：具有CPU寄存器的数据处理系统，用于寄存数据传输与主存储器的数据传输重叠
公开(公告)号：US4630195A
公开(公告)日：1986-12-16
申请号：US615984
申请日：1984-05-31
申请人： Phillip D. Hester , William M. Johnson
发明人： Phillip D. Hester , William M. Johnson
IPC分类号： G06F9/30 , G06F13/12 , G06F13/36 , G06F13/38 , G06F13/42 , G06F13/00
CPC分类号： G06F13/423 , G06F13/122
摘要： The present invention is directed to a conventional data processing system having a CPU and at least one external unit such as the main storage unit acquiring data from or providing data to the CPU and I/O bus for the transfer of data between the CPU and the external unit. The apparatus of the present invention provides for transfers to and from this external unit, e.g., main storage being overlapped with a register to register data transfer routinely carried out in the CPU to implement various CPU operations and computation functions. The CPU includes apparatus for transferring data to or from said external unit over the I/O bus during synchronized time cycles. The CPU also includes local storage apparatus which comprise a plurality of registers as well as expedients for transferring data from register to register. Control apparatus controls the register to register data transfer so that such transfers are conducted during time cycles coincident with the transfer of data to or from the external storage unit. Thus, the register to register data transfers within the CPU are overlapped with the data transfers over the I/O bus to main storage. The data transfers to and from main storage are generally considerably longer that the simpler register to register data transfer. The apparatus may be operated so that several register to register transfers may take place during the time required for a transfer of data to or from the external storage unit. The present invention further includes means for dynamically determining data dependencies between the register to register transfers and the I/O bus transfers.
摘要翻译：本发明涉及一种具有CPU和至少一个外部单元的常规数据处理系统，所述至少一个外部单元例如主存储单元从CPU获取数据或向CPU和I / O总线提供数据，用于在CPU和CPU之间传送数据外部单元本发明的装置提供到外部单元的传输，例如主存储器与寄存器重叠以在CPU中定期执行的数据传输，以实现各种CPU操作和计算功能。 CPU包括用于在同步的时间周期期间通过I / O总线向所述外部单元传送数据或从所述外部单元传送数据的装置。 CPU还包括本地存储装置，其包括多个寄存器以及用于将数据从寄存器传送到寄存器的权限。控制装置控制寄存器进行寄存器数据传输，以便在与向外部存储单元传输数据的时间周期内进行这种传送。因此，在CPU内注册数据传输的寄存器与通过I / O总线传送到主存储器的数据重叠。数据传输到主存储器的数据传输通常比寄存器更简单的数据传输更长。可以操作该装置，使得可以在将数据传送到外部存储单元或从外部存储单元传送所需的时间期间发生几个寄存器到寄存器传送。本发明还包括用于动态地确定寄存器到寄存器传输和I / O总线传输之间的数据依赖性的装置。

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