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1. 发明申请

US20090096501A1 APPARATUS AND METHOD FOR PREVENTING SNAP BACK IN INTEGRATED CIRCUITS 有权
标题翻译：用于防止集成电路中的反馈的装置和方法
公开(公告)号：US20090096501A1
公开(公告)日：2009-04-16
申请号：US11870322
申请日：2007-10-10
申请人： Philip Ng , Sai Kai Tsang , Kris Li , Liqi Wang , Jinshu Son
发明人： Philip Ng , Sai Kai Tsang , Kris Li , Liqi Wang , Jinshu Son
IPC分类号： H03K3/356
CPC分类号： H03K3/356182 , H03K3/013
摘要： A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on.
摘要翻译：一种用于防止在包括至少一个具有与其相关联的寄生双极晶体管的MOS晶体管的电路中的回耦的方法包括将包括至少一个MOS晶体管的至少一个源极/漏极节点的电路节点耦合到偏置电压电路以及使所述偏置电压电路向所述至少一个MOS晶体管的所述至少一个源极/漏极节点提供电位，所述电位具有选择的幅度以防止所述寄生双极晶体管导通。

2. 发明授权

US07692483B2 Apparatus and method for preventing snap back in integrated circuits 有权
标题翻译：集成电路中防止闪回的装置和方法
公开(公告)号：US07692483B2
公开(公告)日：2010-04-06
申请号：US11870322
申请日：2007-10-10
申请人： Philip Ng , Sai Kai Tsang , Kris Li , Liqi Wang , Jinshu Son
发明人： Philip Ng , Sai Kai Tsang , Kris Li , Liqi Wang , Jinshu Son
IPC分类号： H03H3/356
CPC分类号： H03K3/356182 , H03K3/013
摘要： A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on.
摘要翻译：一种用于防止在包括至少一个具有与其相关联的寄生双极晶体管的MOS晶体管的电路中的回耦的方法包括将包括至少一个MOS晶体管的至少一个源极/漏极节点的电路节点耦合到偏置电压电路以及使所述偏置电压电路向所述至少一个MOS晶体管的所述至少一个源极/漏极节点提供电位，所述电位具有选择的幅度以防止所述寄生双极晶体管导通。

3. 发明申请

US20070266280A1 Method and Apparatus to Test the Power-on-Reset Trip Point of an Integrated Circuit 有权
标题翻译：用于测试集成电路的上电复位跳变点的方法和装置
公开(公告)号：US20070266280A1
公开(公告)日：2007-11-15
申请号：US11278223
申请日：2006-03-31
申请人： Philip Ng , Jinshu Son , Liqi Wang , Johnny Chan
发明人： Philip Ng , Jinshu Son , Liqi Wang , Johnny Chan
IPC分类号： G01R31/28
CPC分类号： G01R31/40 , G01R31/3004
摘要： Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.
摘要翻译：用于测试集成电路中的上电复位电路的电路包括耦合到集成电路的第一I / O焊盘的高电压检测器。集成电路中的上电复位电路具有耦合到由高电压供电的驱动器电路的输出。集成电路的第二I / O焊盘耦合到驱动器电路的输出端。可以通过集成电路的第三I / O焊盘上提供的信号使能驱动器电路。

4. 发明申请

US20060023549A1 Fuse data storage system using core memory 有权
公开(公告)号：US20060023549A1
公开(公告)日：2006-02-02
申请号：US10910038
申请日：2004-08-02
申请人： Jinshu Son , Liqi Wang , Minh Le , Philip Ng
发明人： Jinshu Son , Liqi Wang , Minh Le , Philip Ng
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C16/20 , G11C2216/30
摘要： Fuse data used to configure ancillary circuits used with a non-volatile serial memory core are stored in locations within the memory core. As a first opcode or word is sent on a serial bus to the memory, a logic circuit intercepts the word and generates read fuse enable pulses that fetch the fuse data and configure the ancillary circuits before the last bit of the first command byte arrives. If a read operation is designated, the memory circuits are configured to read. If a write operation is designated, further fuse data is fetched from the memory core to configure ancillary circuits for writing. The fuse data is written to the memory core at the time of circuit manufacture thereby obviating the need for separate storage locations.

5. 发明授权

US07519486B2 Method and apparatus to test the power-on-reset trip point of an integrated circuit 有权
标题翻译：测试集成电路的上电复位跳变点的方法和装置
公开(公告)号：US07519486B2
公开(公告)日：2009-04-14
申请号：US11278223
申请日：2006-03-31
申请人： Philip Ng , Jinshu Son , Liqi Wang , Johnny Chan
发明人： Philip Ng , Jinshu Son , Liqi Wang , Johnny Chan
IPC分类号： G06F19/00 , G01R19/00
CPC分类号： G01R31/40 , G01R31/3004
摘要： Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.
摘要翻译：用于测试集成电路中的上电复位电路的电路包括耦合到集成电路的第一I / O焊盘的高电压检测器。集成电路中的上电复位电路具有耦合到由高电压供电的驱动器电路的输出。集成电路的第二I / O焊盘耦合到驱动器电路的输出端。可以通过集成电路的第三I / O焊盘上提供的信号使能驱动器电路。

6. 发明申请

US20070237013A1 Indirect measurement of negative margin voltages in endurance testing of EEPROM cells 有权
标题翻译：在EEPROM单元的耐久性测试中间接测量负余量电压
公开(公告)号：US20070237013A1
公开(公告)日：2007-10-11
申请号：US11393551
申请日：2006-03-29
申请人： Philip Ng , Minh Le , Liqi Wang , Jinshu Son
发明人： Philip Ng , Minh Le , Liqi Wang , Jinshu Son
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C16/04 , G11C29/50004
摘要： An electronic test structure and method for testing non-volatile memory cells. The structure includes a first transistor coupled in series to a floating gate transistor whereby a source of the first transistor is coupled to a positive power supply voltage and a source of the floating gate transistor is coupled to a power supply ground. A gate of the first transistor is further coupled to a source of the first transistor. A second transistor is coupled in series with a memory cell with a source of the second transistor coupled to a positive power supply voltage and a gate of the second transistor is coupled to the drain of the first transistor.
摘要翻译：用于测试非易失性存储单元的电子测试结构和方法。该结构包括与浮栅晶体管串联耦合的第一晶体管，由此第一晶体管的源极耦合到正电源电压，并且浮栅晶体管的源极耦合到电源地。第一晶体管的栅极进一步耦合到第一晶体管的源极。第二晶体管与存储单元串联耦合，其中第二晶体管的源极耦合到正电源电压，第二晶体管的栅极耦合到第一晶体管的漏极。

7. 发明申请

US20060280020A1 Memory data access scheme 有权
标题翻译：内存数据访问方案
公开(公告)号：US20060280020A1
公开(公告)日：2006-12-14
申请号：US11151332
申请日：2005-06-13
申请人： Jinshu Son , Liqi Wang , Minh Le , Philip Ng
发明人： Jinshu Son , Liqi Wang , Minh Le , Philip Ng
IPC分类号： G11C8/00
CPC分类号： G11C7/12 , G11C7/18 , G11C2207/002
摘要： A bitline selection network is composed of a plurality of bitlines and a plurality of global bitlines. The bitlines are grouped into bytes with eight bitlines per byte. The bitlines provide access to memory cells for read and write operations. A bitline is connected to a global bitline through a bitline select transistor. Each of the bitline select transistors is activated one at a time by a bitline select controller. Activation of each bitline select transistor provides a connection to a source line, which in turn connects to a sense amplifier and a write data loading logic block. The sense amplifier and the write data loading logic block are used in read and write operations respectively.
摘要翻译：位线选择网络由多个位线和多个全局位线组成。每个字节将位线分成8个位线的字节。位线提供对存储器单元的访问以进行读取和写入操作。位线通过位线选择晶体管连接到全局位线。每个位线选择晶体管由位线选择控制器一次激活。每个位线选择晶体管的激活提供与源极线的连接，源极线又连接到读出放大器和写入数据加载逻辑块。读写放大器和写数据加载逻辑块分别用于读写操作。

8. 发明申请

US20070121382A1 Circuit to control voltage ramp rate 有权
标题翻译：电路控制电压斜坡率
公开(公告)号：US20070121382A1
公开(公告)日：2007-05-31
申请号：US11291606
申请日：2005-11-30
申请人： Johnny Chan , Philip Ng , Alan Renninger , Jinshu Son , Jeffrey Tsai , Tin-Wai Wong , Tsung-Ching Wu
发明人： Johnny Chan , Philip Ng , Alan Renninger , Jinshu Son , Jeffrey Tsai , Tin-Wai Wong , Tsung-Ching Wu
IPC分类号： G11C11/34
CPC分类号： G11C16/12
摘要： A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.
摘要翻译：一种编程电路和方法，用于以增量的方式对受控或预定的电压脉冲施加电荷转移到非易失性存储单元的浮置栅极，或者从非易失性存储单元的浮动栅极流出，以控制栅极氧化物两端的整体电压。高于传输阈值电压的电压（例如高于隧道阈值电压）以逐步电荷转移方式施加到浮动栅极或从浮动栅极施加到低于薄氧化物损伤阈值的电压极限。控制整体电压可避免氧化物破坏，提高可靠性。

9. 发明申请

US20070247184A1 SERIAL COMMUNICATIONS BUS WITH ACTIVE PULLUP 有权
标题翻译：串行通信总线与主动上拉
公开(公告)号：US20070247184A1
公开(公告)日：2007-10-25
申请号：US11379473
申请日：2006-04-20
申请人： Philip Ng , Jinshu Son
发明人： Philip Ng , Jinshu Son
IPC分类号： H03K19/003
CPC分类号： H03K19/01721 , H03K19/01742
摘要： A dual-wire communications bus circuit, compatible with existing two-wire bus protocols, includes a first and second part of the communications bus circuit to couple to a communications bus. The bus has a first line for carrying data signals from a master device to one or more slave devices and a second line to carry a clock signal between the devices A pullup resistor is located in each part of the communications bus circuit; the pullup resistor in the first part couples to the first line of the communications bus and the pullup resistor in the second part couples to the second line of the communications bus. To improve data throughput and reduce noise, an active pullup device, working in conjunction with the pullup resistor, is located in each part of the communications bus circuit, providing a high logic level on at least one of the communications bus lines.
摘要翻译：与现有的双线总线协议兼容的双线通信总线电路包括通信总线电路的第一和第二部分以耦合到通信总线。总线具有用于承载来自主设备的数据信号到一个或多个从设备的第一行，以及用于在设备之间携带时钟信号的第一线路上拉电阻器位于通信总线电路的每个部分中; 第一部分中的上拉电阻耦合到通信总线的第一行，并且第二部分中的上拉电阻耦合到通信总线的第二行。为了提高数据吞吐量并降低噪声，与通信总线电路的每个部分配置的与上拉电阻一起工作的有源上拉器件位于通信总线电路的每个部分中，在至少一个通信总线上提供高逻辑电平。

10. 发明申请

US20070030729A1 METHOD OF SENSING AN EEPROM REFERENCE CELL 有权
标题翻译：传感EEPROM参考电池的方法
公开(公告)号：US20070030729A1
公开(公告)日：2007-02-08
申请号：US11198469
申请日：2005-08-05
申请人： Johnny Chan , Jinshu Son , Philip Ng
发明人： Johnny Chan , Jinshu Son , Philip Ng
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/28
摘要： An array of memory cells having a predetermined group of storage cells, arranged in a row, also have an arrangement of one or more reference cells fabricated to be adjacent to or proximate to the row of storage cells. The reference cells are written to, erased, or programmed when the storage cells are written to, erased, or programmed. The same number of write, erase, or program cycles and the proximity of the reference cells to the storage cells maintain an operational matching of the storage cells and reference cells.
摘要翻译：排列成行的具有预定组的存储单元的存储单元阵列还具有制造为与存储单元行相邻或邻近的一个或多个参考单元的布置。当存储单元写入，擦除或编程时，参考单元被写入，擦除或编程。相同数量的写，擦除或程序周期以及参考单元与存储单元的接近度保持了存储单元和参考单元的操作匹配。

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