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1. 发明授权

US06799261B2 Memory interface with fractional addressing 失效
$Memory interface with fractional addressing$
标题翻译：具有分数寻址的存储器接口
公开(公告)号：US06799261B2
公开(公告)日：2004-09-28
申请号：US10184582
申请日：2002-06-28
申请人： Philip E. May , Kent Donald Moat , Raymond B. Essick, IV , Silviu Chiricescu , Brian Jeffrey Lucas , James M. Norris , Michael Allen Schuette , Ali Saidi
发明人： Philip E. May , Kent Donald Moat , Raymond B. Essick, IV , Silviu Chiricescu , Brian Jeffrey Lucas , James M. Norris , Michael Allen Schuette , Ali Saidi
IPC分类号： G06F1200
CPC分类号： G06F9/3552 , G06F9/345 , G06F12/04
摘要： A memory interface device (100) providing a fractional address interface between a data processor (104) and a memory system (102) and a method for retrieving intermediate data values from a memory system using fractional addressing. The device includes an address generator (108) for generating first and second memory addresses, the first memory address being less than or equal to a specified fractional address, the second memory address being greater than or equal to the fractional address. The device also includes a memory access unit (110) coupled to the address generator (108) for retrieving first and second data values from the memory system (102) at the first and second memory addresses, respectively. The device also includes a data access unit (112) for interpolating between the first and second data values and passing the interpolated value to the data processor (104). The memory interface has application in a variety of data processing systems, including digital signal processors and streaming vector processors.
摘要翻译：在数据处理器（104）和存储器系统（102）之间提供分数地址接口的存储器接口设备（100）以及用于使用分数寻址从存储器系统检索中间数据值的方法。该设备包括用于产生第一和第二存储器地址的地址发生器（108），第一存储器地址小于或等于指定的分数地址，第二存储器地址大于或等于分数地址。该设备还包括耦合到地址发生器（108）的存储器访问单元（110），用于分别在第一和第二存储器地址处从存储器系统（102）检索第一和第二数据值。该装置还包括用于在第一和第二数据值之间进行内插并将内插值传递给数据处理器（104）的数据访问单元（112）。存储器接口在各种数据处理系统中具有应用，包括数字信号处理器和流媒体矢量处理器。

2. 发明授权

US07159099B2 Streaming vector processor with reconfigurable interconnection switch 失效
标题翻译：具有可重配置互连交换机的流媒体向量处理器
公开(公告)号：US07159099B2
公开(公告)日：2007-01-02
申请号：US10184583
申请日：2002-06-28
申请人： Brian Geoffrey Lucas , Philip E. May , Kent Donald Moat , Raymond B. Essick, IV , Silviu Chiricescu , James M. Norris , Michael Allen Schuette , Ali Saidi
发明人： Brian Geoffrey Lucas , Philip E. May , Kent Donald Moat , Raymond B. Essick, IV , Silviu Chiricescu , James M. Norris , Michael Allen Schuette , Ali Saidi
IPC分类号： G06F15/00
CPC分类号： G06F9/3552 , G06F9/30036 , G06F9/345 , G06F9/3455 , G06F9/3824 , G06F9/383 , G06F9/3877 , G06F9/3879 , G06F15/7867 , G06F15/8061
摘要： A re-configurable, streaming vector processor (100) is provided which includes a number of function units (102), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch (104) and a micro-sequencer (118). The re-configurable interconnection switch (104) includes one or more links, each link operable to couple an output of a function unit (102) to an input of a function unit (102) as directed by the micro-sequencer (118). The vector processor may also include one or more input-stream units (122) for retrieving data from memory. Each input-stream unit is directed by a host processor and has a defined interface (116) to the host processor. The vector processor also includes one or more output-stream units (124) for writing data to memory or to the host processor. The defined interface of the input-stream and output-stream units forms a first part of the programming model. The instructions stored in a memory, in the sequence that direct the re-configurable interconnection switch, form a second part of the programming model.
摘要翻译：提供了可重新配置的流向量处理器（100），其包括多个功能单元（102），每个功能单元（102）具有用于接收数据值的一个或多个输入和用于提供数据值的输出，可重新配置的互连开关 104）和微定序器（118）。可重配置互连开关（104）包括一个或多个链路，每个链路可操作以在功能单元（102）的输出端与微定序器（118）指导的功能单元（102）的输入耦合。向量处理器还可以包括用于从存储器检索数据的一个或多个输入流单元（122）。每个输入流单元由主处理器引导，并且具有到主机处理器的定义的接口（116）。矢量处理器还包括用于将数据写入存储器或主处理器的一个或多个输出流单元（124）。输入流和输出流单元的定义接口形成编程模型的第一部分。存储在存储器中的指令以指导可重新配置的互连交换机的顺序形成编程模型的第二部分。

3. 发明授权

US06934938B2 Method of programming linear graphs for streaming vector computation 失效
标题翻译：用于流矢量计算的线性图的编程方法
公开(公告)号：US06934938B2
公开(公告)日：2005-08-23
申请号：US10184743
申请日：2002-06-28
申请人： Philip E. May , Kent Donald Moat , Raymond B. Essick, IV , Silviu Chiricescu , Brian Geoffrey Lucas , James M. Norris , Michael Allen Schuette , Ali Saidi
发明人： Philip E. May , Kent Donald Moat , Raymond B. Essick, IV , Silviu Chiricescu , Brian Geoffrey Lucas , James M. Norris , Michael Allen Schuette , Ali Saidi
IPC分类号： G06F20060101 , G06F9/44 , G06F9/45
CPC分类号： G06F8/314
摘要： A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each input of the data-flow graph, a computational instruction is generated for each node of the data-flow graph, and a sink instruction is generated for each output of the data-flow graph. The computational instruction for a node includes a descriptor of an operation performed at the node and a descriptor of each instruction that produces an input to the node. The formatted description is a sequential instruction list comprising source instructions, computational instructions and sink instructions. Each instruction has an instruction identifier and the descriptor of each instruction that produces an input to the node is the instruction identifier. The computer is directed by a program of instructions to implement a computation representable by a data-flow graph.
摘要翻译：一种用于产生由数据流图和计算机表示的计算的格式化描述的方法，用于执行如此描述的计算。为数据流图的每个输入生成源指令，为数据流图的每个节点生成计算指令，并为数据流图的每个输出生成汇编指令。节点的计算指令包括在节点处执行的操作的描述符和产生到该节点的输入的每条指令的描述符。格式化的描述是包括源指令，计算指令和汇指令的顺序指令列表。每个指令都有一个指令标识符，并且每个指令的描述符产生一个到该节点的输入是指令标识符。计算机由指令程序引导以实现由数据流图表示的计算。

4. 发明授权

US07140019B2 Scheduler of program instructions for streaming vector processor having interconnected functional units 失效
标题翻译：具有互连功能单元的流媒体处理器的程序指令调度器
公开(公告)号：US07140019B2
公开(公告)日：2006-11-21
申请号：US10184772
申请日：2002-06-28
申请人： Philip E. May , Kent Donald Moat , Raymond B. Essick, IV , Silviu Chiricescu , Brian Geoffrey Lucas , James M. Norris , Michael Allen Schuette , Ali Saidi
发明人： Philip E. May , Kent Donald Moat , Raymond B. Essick, IV , Silviu Chiricescu , Brian Geoffrey Lucas , James M. Norris , Michael Allen Schuette , Ali Saidi
IPC分类号： G06F9/50 , G06F9/44
CPC分类号： G06F8/445
摘要： A method for scheduling a computation for execution on a computer with a number of interconnected functional units. The computation is representable by a data-flow graph with a number of nodes connected by edge. A loop-period of the computation is calculated and the nodes are scheduled for throughput by assigning an execution cycle and a functional unit to each node of the data-flow graph. The scheduling of flexible nodes is adjusted to minimize the number of interconnections required in each execution cycle. The edges of the data-flow graph are allocated to one or more of the interconnections between functional units. The scheduling method may be used, for example, to optimize the interconnection fabric design for an ASIC or as part of a compiler for a re-configurable streaming vector processor.
摘要翻译：一种用于在具有多个互连的功能单元的计算机上调度用于执行的计算的方法。该计算可以由具有多个通过边缘连接的节点的数据流图形表示。计算计算的循环周期，并通过为数据流图的每个节点分配执行周期和功能单元来调度节点的吞吐量。调整灵活节点的调度以最小化每个执行周期中所需的互连数量。数据流图的边缘被分配给功能单元之间的一个或多个互连。例如，可以使用调度方法来优化ASIC的互连结构设计或作为用于可重新配置的流向量处理器的编译器的一部分。

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