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1. 发明授权

US07902661B2 Integrated circuit micro-module 有权
标题翻译：集成电路微模块
公开(公告)号：US07902661B2
公开(公告)日：2011-03-08
申请号：US12643924
申请日：2009-12-21
申请人： Peter Smeys , Peter Johnson , Peter Deane , Reda R. Razouk
发明人： Peter Smeys , Peter Johnson , Peter Deane , Reda R. Razouk
IPC分类号： H01L23/04 , H01L23/12 , H01L23/053 , H01L23/23
CPC分类号： H01L23/5389 , H01L21/4853 , H01L21/486 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3121 , H01L23/49822 , H01L23/49827 , H01L23/5385 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2221/68377 , H01L2224/24137 , H01L2224/24145 , H01L2224/24227 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/01003 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2224/82 , H01L2924/00
摘要： Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.
摘要翻译：描述了用于形成集成电路封装的各种装置和方法。本发明的一个方面涉及一种集成电路封装，其中一个或多个集成电路嵌入在基片中并被一层可光成像的环氧树脂覆盖。基板可以由各种材料制成，包括硅，石英和玻璃。集成电路位于衬底的顶表面中的空腔内。环氧树脂层形成在衬底的顶表面和集成电路的有源面上。在环氧树脂层上形成互连层并与集成电路电耦合。

2. 发明授权

US08822266B2 Integrated circuit micro-module 有权
标题翻译：集成电路微模块
公开(公告)号：US08822266B2
公开(公告)日：2014-09-02
申请号：US13013563
申请日：2011-01-25
申请人： Peter Smeys , Peter Johnson , Peter Deane , Reda R. Razouk
发明人： Peter Smeys , Peter Johnson , Peter Deane , Reda R. Razouk
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44 , H01L23/00 , H01L21/56 , H01L21/683 , H01L23/538 , H01L23/498 , H01L23/31
CPC分类号： H01L23/5389 , H01L21/4853 , H01L21/486 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3121 , H01L23/49822 , H01L23/49827 , H01L23/5385 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2221/68377 , H01L2224/24137 , H01L2224/24145 , H01L2224/24227 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/01003 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2224/82 , H01L2924/00
摘要： Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.
摘要翻译：描述了用于形成集成电路封装的各种装置和方法。本发明的一个方面涉及一种集成电路封装，其中一个或多个集成电路嵌入在基片中并被一层可光成像的环氧树脂覆盖。基板可以由各种材料制成，包括硅，石英和玻璃。集成电路位于衬底的顶表面中的空腔内。环氧树脂层形成在衬底的顶表面和集成电路的有源面上。在环氧树脂层上形成互连层并与集成电路电耦合。

3. 发明申请

US20110115071A1 INTEGRATED CIRCUIT MICRO-MODULE 有权
标题翻译：集成电路微型模块
公开(公告)号：US20110115071A1
公开(公告)日：2011-05-19
申请号：US13013563
申请日：2011-01-25
申请人： Peter Smeys , Peter Johnson , Peter Deane , Reda R. Razouk
发明人： Peter Smeys , Peter Johnson , Peter Deane , Reda R. Razouk
IPC分类号： H01L23/522 , H01L21/56 , H01L21/768
CPC分类号： H01L23/5389 , H01L21/4853 , H01L21/486 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3121 , H01L23/49822 , H01L23/49827 , H01L23/5385 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2221/68377 , H01L2224/24137 , H01L2224/24145 , H01L2224/24227 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/01003 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2224/82 , H01L2924/00
摘要： Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.
摘要翻译：描述了用于形成集成电路封装的各种装置和方法。本发明的一个方面涉及一种集成电路封装，其中一个或多个集成电路嵌入在基片中并被一层可光成像的环氧树脂覆盖。基板可以由各种材料制成，包括硅，石英和玻璃。集成电路位于衬底的顶表面中的空腔内。环氧树脂层形成在衬底的顶表面和集成电路的有源面上。在环氧树脂层上形成互连层并与集成电路电耦合。

4. 发明授权

US5179031A Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide 失效
标题翻译：使用在薄栅极氧化物上使用相同的多晶硅蚀刻来制造多晶硅发射极和多晶硅栅极的方法
公开(公告)号：US5179031A
公开(公告)日：1993-01-12
申请号：US555345
申请日：1990-07-19
申请人： Michael P. Brassington , Reda R. Razouk , Monir H. El-Diwany , Prateep Tuntasood
发明人： Michael P. Brassington , Reda R. Razouk , Monir H. El-Diwany , Prateep Tuntasood
IPC分类号： H01L21/28 , H01L21/311 , H01L21/8249 , H01L27/06
CPC分类号： H01L21/31116 , H01L21/28035 , H01L21/8249 , H01L27/0623 , Y10S148/009
摘要： A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.
摘要翻译：使用单个制造工艺同时制造双极和MOS器件的方法。在本发明的一个实施例中，硅衬底被分为双极和MOS区。在硅衬底上热生长厚度在大约150埃至300埃范围内的薄层栅极氧化物。厚度在大约500埃至1000埃范围内的多晶硅薄层沉积在栅极氧化物层上，以在随后的处理期间保护栅极氧化物层。从形成发射极的双极区域去除薄多晶硅层和栅极氧化物层。为了在蚀刻期间保持栅极氧化物层的完整性，在栅极氧化物蚀刻期间保留在多晶硅蚀刻期间使用的光致抗蚀剂掩模，并且在缓冲的氧化物溶液中蚀刻栅极氧化物。然后将厚的多晶硅层沉积在硅衬底的双极和MOS区上，并且掩模和蚀刻衬底以形成双极和MOS器件的发射极和栅极。

5. 发明授权

US5001081A Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide 失效
标题翻译：使用在薄栅极氧化物上使用相同的多晶硅蚀刻来制造多晶硅发射极和多晶硅栅极的方法
公开(公告)号：US5001081A
公开(公告)日：1991-03-19
申请号：US418946
申请日：1989-10-06
申请人： Prateep Tuntasood , Michael P. Brassington , Reda R. Razouk , Monir H. El-Diwany
发明人： Prateep Tuntasood , Michael P. Brassington , Reda R. Razouk , Monir H. El-Diwany
IPC分类号： H01L21/28 , H01L21/311 , H01L21/8249 , H01L27/06
CPC分类号： H01L27/0623 , H01L21/28035 , H01L21/31116 , H01L21/8249 , Y10S148/009
摘要： A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.
摘要翻译：使用单个制造工艺同时制造双极和MOS器件的方法。在本发明的一个实施例中，硅衬底被分为双极和MOS区。在硅衬底上热生长厚度在大约150埃至300埃范围内的薄层栅极氧化物。厚度在大约500埃至1000埃范围内的多晶硅薄层沉积在栅极氧化物层上，以在随后的处理期间保护栅极氧化物层。从形成发射极的双极区域去除薄多晶硅层和栅极氧化物层。为了在蚀刻期间保持栅极氧化物层的完整性，在栅极氧化物蚀刻期间保留在多晶硅蚀刻期间使用的光致抗蚀剂掩模，并且在缓冲的氧化物溶液中蚀刻栅极氧化物。然后将厚的多晶硅层沉积在硅衬底的双极和MOS区上，并且掩模和蚀刻衬底以形成双极和MOS器件的发射极和栅极。

6. 发明授权

US08686332B2 Optically-controlled shunt circuit for maximizing photovoltaic panel efficiency 有权
标题翻译：用于最大限度地提高光伏面板效率的光控并联电路
公开(公告)号：US08686332B2
公开(公告)日：2014-04-01
申请号：US13042173
申请日：2011-03-07
申请人： Reda R. Razouk , Peter J. Hopper
发明人： Reda R. Razouk , Peter J. Hopper
IPC分类号： G01C21/02 , H01L31/042
CPC分类号： H01L31/02021 , H03K17/78 , Y02E10/50
摘要： An optically-controlled shunt (OCS) circuit includes a switch and a light sampler. The light sampler is coupled to the switch and is configured to sample light at a photovoltaic (PV) cell corresponding to the OCS circuit and to turn on the switch when the sampled light comprises insufficient light for the PV cell. The light sampler may also be configured to turn off the switch when the sampled light comprises sufficient light for the PV cell. The light sampler may further be configured to partially turn on the switch when the sampled light comprises adequate light for the PV cell and to turn off the switch when the sampled light comprises full light for the PV cell. The switch could include a transistor, and the light sampler could include a photodiode.
摘要翻译：光控分路（OCS）电路包括开关和光采样器。光采样器耦合到开关并且被配置为在对应于OCS电路的光伏（PV）单元处采样光，并且当采样的光包括用于PV电池的不足的光时，导通开关。光采样器还可以被配置为当采样的光包括用于PV电池的足够的光时关闭开关。当采样的光包括用于PV电池的足够的光并且当采样的光包括用于PV电池的全光时关闭开关，光采样器还可以被配置为部分地接通开关。开关可以包括晶体管，并且光采样器可以包括光电二极管。

7. 发明授权

US5581110A Integrated circuit with trenches and an oxygen barrier layer 失效
标题翻译：具有沟槽和氧阻隔层的集成电路
公开(公告)号：US5581110A
公开(公告)日：1996-12-03
申请号：US516114
申请日：1995-08-17
申请人： Reda R. Razouk , Kulwant S. Egan , Wipawan Yindeepol , Waclaw C. Koscielniak
发明人： Reda R. Razouk , Kulwant S. Egan , Wipawan Yindeepol , Waclaw C. Koscielniak
IPC分类号： H01L21/3105 , H01L21/334 , H01L21/762 , H01L27/12
CPC分类号： H01L29/66181 , H01L21/3105 , H01L21/76264 , H01L21/76275 , H01L21/76286
摘要： A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.
摘要翻译：公开了具有与半导体衬底的表面相交的壁和衬在壁上的氧化/扩散阻挡层的沟槽。氧化/扩散屏障在沟槽的边缘上延伸，以防止例如沟槽中的应力缺陷和沟槽内的垂直鸟嘴形成。在沟槽内沉积诸如多晶硅的填充材料，随后在沟槽上沉积平坦化层。在施加热量之后，平坦化层流动以在沟槽上形成平坦化层。使用高压磷硅玻璃作平坦化层，平坦化层在低温下适当地流动短时间。

8. 发明申请

US20120228480A1 OPTICALLY-CONTROLLED SHUNT CIRCUIT FOR MAXIMIZING PHOTOVOLTAIC PANEL EFFICIENCY 有权
标题翻译：用于最大化光伏面板效率的光控分流电路
公开(公告)号：US20120228480A1
公开(公告)日：2012-09-13
申请号：US13042173
申请日：2011-03-07
申请人： Reda R. Razouk , Peter J. Hopper
发明人： Reda R. Razouk , Peter J. Hopper
IPC分类号： H03K17/78 , H01L31/02
CPC分类号： H01L31/02021 , H03K17/78 , Y02E10/50
摘要： An optically-controlled shunt (OCS) circuit includes a switch and a light sampler. The light sampler is coupled to the switch and is configured to sample light at a photovoltaic (PV) cell corresponding to the OCS circuit and to turn on the switch when the sampled light comprises insufficient light for the PV cell. The light sampler may also be configured to turn off the switch when the sampled light comprises sufficient light for the PV cell. The light sampler may further be configured to partially turn on the switch when the sampled light comprises adequate light for the PV cell and to turn off the switch when the sampled light comprises full light for the PV cell. The switch could include a transistor, and the light sampler could include a photodiode.
摘要翻译：光控分路（OCS）电路包括开关和光采样器。光采样器耦合到开关并且被配置为在对应于OCS电路的光伏（PV）单元处采样光，并且当采样的光包括用于PV电池的不足的光时，导通开关。光采样器还可以被配置为当采样的光包括用于PV电池的足够的光时关闭开关。当采样的光包括用于PV电池的足够的光并且当采样的光包括用于PV电池的全光时关闭开关，光采样器还可以被配置为部分地接通开关。开关可以包括晶体管，并且光采样器可以包括光电二极管。

9. 发明授权

US06548323B1 Method of preparing light-sensitive integrated circuits for packaging 有权
标题翻译：制备用于包装的光敏集成电路的方法
公开(公告)号：US06548323B1
公开(公告)日：2003-04-15
申请号：US09629255
申请日：2000-07-31
申请人： Jeffrey R. Perry , Michael E. Thomas , Robert A. Sabsowitz , Reda R. Razouk , Aaron G. Simmons
发明人： Jeffrey R. Perry , Michael E. Thomas , Robert A. Sabsowitz , Reda R. Razouk , Aaron G. Simmons
IPC分类号： H01L2100
CPC分类号： H01L31/0203 , H01L31/18
摘要： A process for preparing a light-sensitive integrated circuit (IC) for packaging that provides a reduced exposure of the light-sensitive IC to light. The process includes providing a semiconductor substrate (e.g., a silicon wafer) with a plurality of light-sensitive ICs formed in/on its upper surface. The lower surface is optionally coated with opaque material. Next, the semiconductor substrate is diced to form individual light-sensitive ICs, each of which has a semiconductor substrate lower surface and semiconductor substrate lateral edges. The semiconductor substrate lateral edges (and optionally backside) are then spray coated with an opaque material (e.g., opaque ink) to form an opaque layer covering the semiconductor substrate lateral edges. The opaque layer prevents light from entering the semiconductor substrate through the lateral edges and interfering with the operation of the light-sensitive IC. The inventive process is simple and inexpensive, employing, for example, piezoelectric injectors to spray coat opaque ink on the semiconductor substrate lateral edges as the individual ICs are conveyed through a pass-through. In addition, processes according to the present invention are independent of the techniques used to manufacture the light-sensitive ICs and, therefore, provide for increased packaging process flexibility and economy.
摘要翻译：一种用于制备用于包装的光敏集成电路（IC）的方法，其将光敏IC的曝光减少到光。该方法包括在其上表面上/上形成有多个感光IC的半导体衬底（例如，硅晶片）。下表面任选地涂覆有不透明材料。接下来，对半导体衬底进行切割以形成各自具有半导体衬底下表面和半导体衬底横向边缘的感光IC。然后用不透明材料（例如不透明油墨）喷涂涂覆半导体衬底的侧边缘（以及可选的背面），以形成覆盖半导体衬底横向边缘的不透明层。不透明层防止光通过横向边缘进入半导体衬底并干扰光敏IC的操作。本发明的方法是简单和便宜的，当单个IC通过通过传送时，使用例如压电喷射器在半导体衬底横向边缘上喷涂不透明油墨。此外，根据本发明的方法独立于用于制造光敏IC的技术，因此提供增加的包装工艺灵活性和经济性。

10. 发明授权

US5911109A Method of forming an integrated circuit including filling and planarizing a trench having an oxygen barrier layer 失效
标题翻译：形成集成电路的方法，包括填充和平坦化具有氧阻隔层的沟槽
公开(公告)号：US5911109A
公开(公告)日：1999-06-08
申请号：US800012
申请日：1997-02-13
申请人： Reda R. Razouk , Kulwant S. Egan , Wipawan Yindeepol , Waclaw C. Koscielniak
发明人： Reda R. Razouk , Kulwant S. Egan , Wipawan Yindeepol , Waclaw C. Koscielniak
IPC分类号： H01L21/3105 , H01L21/334 , H01L21/762 , H01L21/62
CPC分类号： H01L29/66181 , H01L21/3105 , H01L21/76264 , H01L21/76275 , H01L21/76286
摘要： A trench which has walls intersecting a surface of a semiconductor substrate and an oxidation/diffusion barrier layer lining the walls is disclosed. The oxidation/diffusion barrier extends over the edges of the trench to prevent, for example, stress defects in the trench corners and vertical bird's beak formation within the trench. A filler material such as polysilicon is deposited within the trench followed by the deposition of a planarizing layer over the trench. After heat is applied, the planarizing layer flows to form a planarized layer over the trench. Using high pressure and phosphosilicate glass for the planarizing layer, the planarizing layer flows appropriately at low temperatures for short times.
摘要翻译：公开了具有与半导体衬底的表面相交的壁和衬在壁上的氧化/扩散阻挡层的沟槽。氧化/扩散屏障在沟槽的边缘上延伸，以防止例如沟槽中的应力缺陷和沟槽内的垂直鸟嘴形成。在沟槽内沉积诸如多晶硅的填充材料，随后在沟槽上沉积平坦化层。在施加热量之后，平坦化层流动以在沟槽上形成平坦化层。使用高压磷硅玻璃作平坦化层，平坦化层在低温下适当地流动短时间。

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