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1. 发明申请

US20080244224A1 Scheduling a direct dependent instruction 审中-公开
标题翻译：计划直接依赖指令
公开(公告)号：US20080244224A1
公开(公告)日：2008-10-02
申请号：US11729711
申请日：2007-03-29
申请人： Peter Sassone , Jeff Rupley , Bryan Black
发明人： Peter Sassone , Jeff Rupley , Bryan Black
IPC分类号： G06F15/00
CPC分类号： G06F9/3838
摘要： In one embodiment, the present invention includes an apparatus having an instruction selector to select an instruction, where the selector is to store a dependent indicator to indicate a direct dependent consumer instruction of a producer instruction, a decode logic coupled to the instruction selector to receive the dependent indicator when the producer instruction is selected and to generate a wakeup signal for the direct dependent consumer instruction, and wakeup logic to receive the wakeup signal and to indicate that the producer instruction has been selected. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有选择指令的指令选择器的装置，其中选择器将存储依赖指示符以指示生成器指令的直接依赖消费者指令，耦合到指令选择器以接收的解码逻辑当生产者指令被选择并且产生用于直接依赖的消费者指令的唤醒信号时的依赖指示符，以及用于接收唤醒信号并指示已经选择了生产者指令的唤醒逻辑。描述和要求保护其他实施例。

2. 发明申请

US20120089807A1 METHOD AND APPARATUS FOR FLOATING POINT REGISTER CACHING 有权
标题翻译：浮点注册缓存的方法和装置
公开(公告)号：US20120089807A1
公开(公告)日：2012-04-12
申请号：US12900124
申请日：2010-10-07
申请人： Jeff Rupley
发明人： Jeff Rupley
IPC分类号： G06F12/08
CPC分类号： G06F9/384 , G06F9/3013
摘要： The present invention provides a method and apparatus for floating-point register caching. One embodiment of the method includes mapping a first set of architected registers defined by a first instruction set to a memory outside of a plurality of physical registers. The plurality of physical registers are configured to map to the first set, a second set of architected registers defined by a second construction set, and a set of rename registers. This embodiment of the method also includes adding the physical registers corresponding to the first set of architected registers to the set of rename registers.
摘要翻译：本发明提供了一种用于浮点寄存器高速缓存的方法和装置。该方法的一个实施例包括将由第一指令集定义的第一组架构寄存器映射到多个物理寄存器外部的存储器。多个物理寄存器被配置为映射到第一集合，由第二结构集合定义的第二组架构寄存器和一组重命名寄存器。该方法的该实施例还包括将对应于第一组架构寄存器的物理寄存器添加到重命名寄存器集合。

3. 发明授权

US09626190B2 Method and apparatus for floating point register caching 有权
公开(公告)号：US09626190B2
公开(公告)日：2017-04-18
申请号：US12900124
申请日：2010-10-07
申请人： Jeff Rupley
发明人： Jeff Rupley
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/384 , G06F9/3013
摘要： The present invention provides a method and apparatus for floating-point register caching. One embodiment of the method includes mapping a first set of architected registers defined by a first instruction set to a memory outside of a plurality of physical registers. The plurality of physical registers are configured to map to the first set, a second set of architected registers defined by a second construction set, and a set of rename registers. This embodiment of the method also includes adding the physical registers corresponding to the first set of architected registers to the set of rename registers.

4. 发明授权

US08825988B2 Matrix algorithm for scheduling operations 有权
标题翻译：用于调度操作的矩阵算法
公开(公告)号：US08825988B2
公开(公告)日：2014-09-02
申请号：US12945432
申请日：2010-11-12
申请人： Jeff Rupley , Rajagopalan Desikan
发明人： Jeff Rupley , Rajagopalan Desikan
IPC分类号： G06F9/46 , G06F9/48 , G06F9/38
CPC分类号： G06F9/46 , G06F9/30047 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3885 , G06F9/4843
摘要： The present invention provides a method and apparatus for implementing a matrix algorithm for scheduling instructions. One embodiment of the method includes selecting a first subset of instructions so that each instruction in the first subset is the earliest in program order of instructions associated with a corresponding one of a plurality of sub-matrices of a matrix that has a plurality of matrix entries. Each matrix entry indicates the program order of one pair of instructions that are eligible for execution. This embodiment also includes selecting, from the first subset of instructions, the instruction that is earliest in program order based on matrix entries associated with the first subset of instructions.
摘要翻译：本发明提供一种用于实现用于调度指令的矩阵算法的方法和装置。该方法的一个实施例包括选择指令的第一子集，使得第一子集中的每个指令是与具有多个矩阵条目的矩阵的多个子矩阵中的相应一个子矩阵相关联的指令的程序顺序中最早的。每个矩阵条目指示有资格执行的一对指令的程序顺序。该实施例还包括从第一指令子集中选择基于与第一指令子集相关联的矩阵条目以程序顺序最早的指令。

5. 发明授权

US09244841B2 Merging eviction and fill buffers for cache line transactions 有权
标题翻译：合并驱逐和填充缓冲区用于缓存行事务
公开(公告)号：US09244841B2
公开(公告)日：2016-01-26
申请号：US13731292
申请日：2012-12-31
申请人： Jeff Rupley , Tarun Nakra
发明人： Jeff Rupley , Tarun Nakra
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/08 , G06F5/06 , G06F13/16
CPC分类号： G06F12/0811 , G06F5/065 , G06F12/0808 , G06F13/1673
摘要： A processor includes a first cache memory and a bus unit in some embodiments. The bus unit includes a plurality of buffers and is operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory, load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer.
摘要翻译：在一些实施例中，处理器包括第一高速缓冲存储器和总线单元。总线单元包括多个缓冲器，并且可操作以分配用于与要存储在第一高速缓冲存储器中的第一高速缓存行相关联的填充请求的多个缓冲器的选定缓冲器，将填充数据从第一高速缓存行加载到并且将填充数据与从所选择的缓冲器中的第一高速缓冲存储器中取出的驱逐规则数据并行地传送到第一缓存存储器。

6. 发明申请

US20120124345A1 CUMULATIVE CONFIDENCE FETCH THROTTLING 有权
标题翻译：累积信心电流谐波
公开(公告)号：US20120124345A1
公开(公告)日：2012-05-17
申请号：US12946491
申请日：2010-11-15
申请人： Marvin Denman , James Dundas , Bradley Gene Burgess , Jeff Rupley
发明人： Marvin Denman , James Dundas , Bradley Gene Burgess , Jeff Rupley
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3844
摘要： A method and apparatus to utilize a fetching scheme for instructions in a processor to limit the expenditure of power caused by the speculative execution of branch instructions is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes calculating a cumulative confidence measure based on one or more outstanding conditional branch instructions. The method also includes reducing prefetching operations in response to detecting that the cumulative confidence measure is below a first threshold level.
摘要翻译：提供了一种方法和装置，用于利用处理器中的指令的取出方案来限制由分支指令的推测性执行引起的功率消耗。还提供了一种用数据编码的计算机可读存储设备，用于使制造设备适配以创建设备。该方法包括基于一个或多个未完成的条件分支指令来计算累积置信度量度。响应于检测到累积置信度量度低于第一阈值水平，该方法还包括减少预取操作。

7. 发明授权

US09836304B2 Cumulative confidence fetch throttling 有权
公开(公告)号：US09836304B2
公开(公告)日：2017-12-05
申请号：US12946491
申请日：2010-11-15
申请人： Marvin Denman , James Dundas , Bradley Gene Burgess , Jeff Rupley
发明人： Marvin Denman , James Dundas , Bradley Gene Burgess , Jeff Rupley
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3844
摘要： A method and apparatus to utilize a fetching scheme for instructions in a processor to limit the expenditure of power caused by the speculative execution of branch instructions is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes calculating a cumulative confidence measure based on one or more outstanding conditional branch instructions. The method also includes reducing prefetching operations in response to detecting that the cumulative confidence measure is below a first threshold level.

8. 发明授权

US09361103B2 Store replay policy 有权
标题翻译：商店重播政策
公开(公告)号：US09361103B2
公开(公告)日：2016-06-07
申请号：US13667095
申请日：2012-11-02
申请人： David A. Kaplan , Jeff Rupley , Tarun Nakra
发明人： David A. Kaplan , Jeff Rupley , Tarun Nakra
IPC分类号： G06F12/00 , G06F9/30 , G06F9/38 , G06F12/08
CPC分类号： G06F9/30065 , G06F9/30043 , G06F9/3861 , G06F12/0802 , G06F12/0815
摘要： A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided.
摘要翻译：提供了一种用于执行可缓存存储的方法。该方法包括基于高速缓存行的状态和存储指令的执行阶段确定是否重放存储指令以重新获取一个或多个高速缓存行。响应于确定重播商店指令而重放存储指令。提供了一种装置，其包括可配置以基于高速缓存行的状态和存储指令的执行阶段来确定是否重播存储指令以重新获取一个或多个高速缓存行的存储队列（SQ）。提供了用于使制造设备适应制造装置的计算机可读存储装置。

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