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1. 发明申请

US20090170279A1 METHOD OF PREPARING ACTIVE SILICON REGIONS FOR CMOS OR OTHER DEVICES 有权
标题翻译：制备CMOS或其他器件的活性硅区域的方法
公开(公告)号：US20090170279A1
公开(公告)日：2009-07-02
申请号：US11967708
申请日：2007-12-31
申请人： Seiyon Kim , Peter L. D. Chang , Ibrahim Ban , Willy Rachmady
发明人： Seiyon Kim , Peter L. D. Chang , Ibrahim Ban , Willy Rachmady
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L29/78648
摘要： A method of preparing active silicon regions for CMOS devices includes providing a structure including a silicon substrate (210, 410) having formed thereon first and second silicon diffusion lines (110, 420), both of which include first and second silicon layers (211, 213, 421, 423), a silicon germanium layer (212, 422), and an electrically insulating layer (214, 424). The method further includes forming an oxide layer (430) in first and second regions of the structure, forming a polysilicon layer (510) over the oxide layer, removing the polysilicon layer from the first region and depositing oxide (610) therein in order to form an oxide anchor, removing the polysilicon layer from the second region, removing the silicon germanium layer, filling the first and second gaps with an electrically insulating material (910), and depositing oxide in the second region.
摘要翻译：一种制备用于CMOS器件的有源硅区域的方法包括提供包括其上形成有第一和第二硅扩散线（110,420）的硅衬底（210,410）的结构，它们都包括第一和第二硅层（211,420） 213,421,423），硅锗层（212,422）和电绝缘层（214,424）。所述方法还包括在所述结构的第一和第二区域中形成氧化物层（430），在所述氧化物层上形成多晶硅层（510），从所述第一区域去除多晶硅层并在其中沉积氧化物（610），以便形成氧化物锚，从第二区域去除多晶硅层，去除硅锗层，用电绝缘材料（910）填充第一和第二间隙，以及在第二区域中沉积氧化物。

2. 发明申请

US20080090348A1 Gate-assisted silicon-on-insulator on bulk wafer and its application to floating body cell memory and transistors 审中-公开
标题翻译：门极辅助绝缘体上的体晶片及其在浮体晶体管中的应用
公开(公告)号：US20080090348A1
公开(公告)日：2008-04-17
申请号：US11540987
申请日：2006-09-28
申请人： Peter L. D. Chang , Willy Rachmady , Seiyon Kim
发明人： Peter L. D. Chang , Willy Rachmady , Seiyon Kim
IPC分类号： H01L21/8238
CPC分类号： H01L21/845 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10897 , H01L27/1211 , H01L29/42392 , H01L29/66795 , H01L29/7841 , H01L29/785
摘要： Embodiments of methods and apparatus for a gate-assisted silicon-on-insulator on bulk wafer and its application to floating body cells are generally described herein. Other embodiments may be described and claimed.
摘要翻译：在本文中一般地描述用于体积晶片上的栅极辅助绝缘体上硅的方法和装置的实施方案及其在浮体电池中的应用。可以描述和要求保护其他实施例。

3. 发明授权

US07560358B1 Method of preparing active silicon regions for CMOS or other devices 有权
标题翻译：为CMOS或其他器件制备活性硅区域的方法
公开(公告)号：US07560358B1
公开(公告)日：2009-07-14
申请号：US11967708
申请日：2007-12-31
申请人： Seiyon Kim , Peter L. D. Chang , Ibrahim Ban , Willy Rachmady
发明人： Seiyon Kim , Peter L. D. Chang , Ibrahim Ban , Willy Rachmady
IPC分类号： H01L27/01
CPC分类号： H01L21/823878 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L29/78648
摘要： A method of preparing active silicon regions for CMOS or other devices includes providing a structure including a silicon substrate (210, 410) having formed thereon first and second silicon diffusion lines (110, 420), both of which include first and second silicon layers (211, 213, 421, 423), a silicon germanium layer (212, 422), and a mask layer (214, 424). The method further includes forming an oxide layer (430) in first and second regions of the structure, forming a polysilicon layer (510) over the oxide layer, removing the polysilicon layer from the first region and depositing oxide (610) therein in order to form an oxide anchor, removing the polysilicon layer from the second region, removing the silicon germanium layer, filling the first and second gaps with an electrically insulating material (910), and depositing oxide in the second region.
摘要翻译：制备用于CMOS或其它器件的活性硅区域的方法包括提供包括在其上形成有第一和第二硅扩散线（110,420）的硅衬底（210,410）的结构，它们都包括第一和第二硅层（ 211,213,421,423），硅锗层（212,422）和掩模层（214,424）。所述方法还包括在所述结构的第一和第二区域中形成氧化物层（430），在所述氧化物层上形成多晶硅层（510），从所述第一区域去除多晶硅层并在其中沉积氧化物（610），以便形成氧化物锚，从第二区域去除多晶硅层，去除硅锗层，用电绝缘材料（910）填充第一和第二间隙，以及在第二区域中沉积氧化物。

4. 发明授权

US09646970B2 Floating body memory cell having gates favoring different conductivity type regions 有权
公开(公告)号：US09646970B2
公开(公告)日：2017-05-09
申请号：US15349862
申请日：2016-11-11
申请人： Peter L. D. Chang , Uygar E. Avci , David Kencke , Ibrahim Ban
发明人： Peter L. D. Chang , Uygar E. Avci , David Kencke , Ibrahim Ban
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/108 , H01L27/092 , H01L29/06 , H01L29/49 , H01L29/51 , H01L29/16
CPC分类号： H01L27/10802 , H01L21/28008 , H01L21/823821 , H01L21/823828 , H01L21/823857 , H01L21/823878 , H01L21/823892 , H01L27/0924 , H01L27/0928 , H01L27/108 , H01L27/10826 , H01L27/10844 , H01L27/10879 , H01L27/1203 , H01L29/0649 , H01L29/0653 , H01L29/16 , H01L29/495 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/66477 , H01L29/66795 , H01L29/78 , H01L29/7841 , H01L29/785 , H01L29/7851 , Y10S257/903
摘要： A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

5. 发明授权

US08373217B2 Epitaxial fabrication of fins for FinFET devices 有权
标题翻译： FinFET器件翅片外延制造
公开(公告)号：US08373217B2
公开(公告)日：2013-02-12
申请号：US13212822
申请日：2011-08-18
申请人： Peter L. D. Chang
发明人： Peter L. D. Chang
IPC分类号： H01L29/66
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A fin for a finFET is described. The fin is a portion of a layer of material, where, another portion of the layer of material resides on a sidewall.
摘要翻译：描述了finFET的翅片。翅片是材料层的一部分，其中材料层的另一部分位于侧壁上。

6. 发明授权

US08268709B2 Independently accessed double-gate and tri-gate transistors in same process flow 有权
标题翻译：独立访问的双栅极和三栅极晶体管在相同的工艺流程中
公开(公告)号：US08268709B2
公开(公告)日：2012-09-18
申请号：US12852408
申请日：2010-08-06
申请人： Peter L. D. Chang , Brian S. Doyle
发明人： Peter L. D. Chang , Brian S. Doyle
IPC分类号： H01L21/3205
CPC分类号： H01L29/785 , H01L21/845 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L29/66545 , H01L29/66795
摘要： A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device.
摘要翻译：描述了在相同工艺流程中制造双栅极和三栅极晶体管的方法。在一个实施例中，在包括半导体主体和绝缘构件的堆叠件上形成牺牲层。在形成栅极限定构件之前，牺牲层被平坦化。在形成栅极限定构件之后，剩余的绝缘构件部分从三栅极器件的半导体本体上方除去，而不是I栅极器件。这有助于在三栅极器件的三侧上形成金属化，以及形成用于I栅极器件的独立栅极。

7. 发明申请

US20110298098A1 EXPITAXIAL FABRICATION OF FINS FOR FINFET DEVICES 有权
标题翻译： FINFET器件FINS的外延制造
公开(公告)号：US20110298098A1
公开(公告)日：2011-12-08
申请号：US13212822
申请日：2011-08-18
申请人： Peter L. D. Chang
发明人： Peter L. D. Chang
IPC分类号： H01L29/06
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A fin for a finFET is described. The fin is a portion of a layer of material, where, another portion of the layer of material resides on a sidewall.
摘要翻译：描述了finFET的翅片。翅片是材料层的一部分，其中材料层的另一部分位于侧壁上。

8. 发明授权

US08058690B2 Integration of planar and tri-gate devices on the same substrate 有权
标题翻译：平面和三栅极器件集成在同一个衬底上
公开(公告)号：US08058690B2
公开(公告)日：2011-11-15
申请号：US12362304
申请日：2009-01-29
申请人： Peter L. D. Chang
发明人： Peter L. D. Chang
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L21/845 , H01L27/1104 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a source from a drain; a first gate electrode formed on the substrate, wherein the first gate electrode overlaps one of the pair of channels on the first diffusion to form a pass-gate transistor; and a second gate electrode formed on the substrate, wherein the second gate electrode overlaps one of the pair of channels of the first diffusion to form a pull-down transistor and overlaps the channel of the second diffusion to form a pull-up transistor, and wherein the pass-gate, pull-down and pull-up transistors are of at least two different constructions. Other embodiments are disclosed and claimed.
摘要翻译：一种包括形成在衬底上的第一扩散器的装置，所述第一扩散部包括一对沟道，每一个沟道将源极与漏极分离; 形成在所述衬底上的第二扩散部，所述第二扩散部包括将源极与漏极分离的沟道; 形成在所述基板上的第一栅电极，其中所述第一栅电极与所述第一扩散层上的所述一对沟道中的一个重叠，以形成栅极晶体管; 以及形成在所述基板上的第二栅电极，其中所述第二栅电极与所述第一扩散层的所述一对沟道中的一个重叠以形成下拉晶体管并与所述第二扩散层的沟道重叠以形成上拉晶体管，以及其中所述通过栅极，下拉和上拉晶体管具有至少两个不同的结构。公开和要求保护其他实施例。

9. 发明申请

US20170062434A1 FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS 审中-公开
标题翻译：具有不同电导率类型区域的浮动体内存单元
公开(公告)号：US20170062434A1
公开(公告)日：2017-03-02
申请号：US15349862
申请日：2016-11-11
申请人： Peter L. D. Chang , Uygar E. Avci , David Kencke , Ibrahim Ban
发明人： Peter L. D. Chang , Uygar E. Avci , David Kencke , Ibrahim Ban
IPC分类号： H01L27/108 , H01L29/16 , H01L29/49 , H01L29/51 , H01L27/092 , H01L29/06
CPC分类号： H01L27/10802 , H01L21/28008 , H01L21/823821 , H01L21/823828 , H01L21/823857 , H01L21/823878 , H01L21/823892 , H01L27/0924 , H01L27/0928 , H01L27/108 , H01L27/10826 , H01L27/10844 , H01L27/10879 , H01L27/1203 , H01L29/0649 , H01L29/0653 , H01L29/16 , H01L29/495 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/66477 , H01L29/66795 , H01L29/78 , H01L29/7841 , H01L29/785 , H01L29/7851 , Y10S257/903
摘要： A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
摘要翻译：描述了一种用于制造浮体记忆单元（FBC）的方法，并且使用其中使用有利于不同导电类型区域的栅极的所得FBC。在一个实施例中，具有更厚绝缘的p型背栅与较薄绝缘的n型前门一起使用。描述了补偿不对准的处理，其允许制造不同的氧化物和栅极材料。

10. 发明授权

US08980707B2 Floating body memory cell having gates favoring different conductivity type regions 有权
标题翻译：具有有利于不同导电类型区域的门的浮体存储单元
公开(公告)号：US08980707B2
公开(公告)日：2015-03-17
申请号：US14028043
申请日：2013-09-16
申请人： Peter L. D. Chang , Uygar E. Avci , David Kencke , Ibrahim Ban
发明人： Peter L. D. Chang , Uygar E. Avci , David Kencke , Ibrahim Ban
IPC分类号： H01L21/8238 , H01L29/78 , H01L27/108 , H01L27/12 , H01L29/66 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/10802 , H01L21/28008 , H01L21/823821 , H01L21/823828 , H01L21/823857 , H01L21/823878 , H01L21/823892 , H01L27/0924 , H01L27/0928 , H01L27/108 , H01L27/10826 , H01L27/10844 , H01L27/10879 , H01L27/1203 , H01L29/0649 , H01L29/0653 , H01L29/16 , H01L29/495 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/66477 , H01L29/66795 , H01L29/78 , H01L29/7841 , H01L29/785 , H01L29/7851 , Y10S257/903
摘要： A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
摘要翻译：描述了一种用于制造浮体记忆单元（FBC）的方法，并且使用其中使用有利于不同导电类型区域的栅极的所得FBC。在一个实施例中，具有更厚绝缘的p型背栅与较薄绝缘的n型前门一起使用。描述了补偿不对准的处理，其允许制造不同的氧化物和栅极材料。

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