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1. 发明授权

US08830360B1 Method and apparatus for optimizing image quality based on scene content 有权
标题翻译：基于场景内容优化图像质量的方法和装置
公开(公告)号：US08830360B1
公开(公告)日：2014-09-09
申请号：US13218152
申请日：2011-08-25
申请人： Peter Jeffrey Burt , Sek Meng Chai , David Chao Zhang , Michael Raymond Piacentino , Gooitzen Siemen van der Wal , Peter Alan Levine , Thomas Lee Vogelsong , John Robertson Tower
发明人： Peter Jeffrey Burt , Sek Meng Chai , David Chao Zhang , Michael Raymond Piacentino , Gooitzen Siemen van der Wal , Peter Alan Levine , Thomas Lee Vogelsong , John Robertson Tower
IPC分类号： H04N5/217 , H04N5/21 , H04N9/78 , G06K9/48
CPC分类号： H04N5/21 , H04N5/23277 , H04N5/243
摘要： A method and apparatus for optimizing image quality based on scene content comprising a sensor for generating a sequence of frames where each frame in the sequence of frames comprises content representing a scene and a digital processor, coupled to the sensor, for performing scene content analysis and for establishing a window defining a number of input frames from the sensor and processed output frames, and for aligning and combining the number of frames in the window to form an output frame, wherein sensor parameters and frame combination parameters are adjusted based on scene content.
摘要翻译：一种用于基于场景内容优化图像质量的方法和装置，包括用于生成帧序列的传感器，其中帧序列中的每个帧包括表示场景的内容和耦合到传感器的数字处理器，用于执行场景内容分析，以及用于建立从传感器和经处理的输出帧定义多个输入帧的窗口，以及用于对齐和组合窗口中的帧数以形成输出帧，其中基于场景内容调整传感器参数和帧组合参数。

2. 发明授权

US06188381B1 Modular parallel-pipelined vision system for real-time video processing 失效
标题翻译：用于实时视频处理的模块化并行流水线视觉系统
公开(公告)号：US06188381B1
公开(公告)日：2001-02-13
申请号：US09002265
申请日：1997-12-31
申请人： Gooitzen Siemen van der Wal , Michael Wade Hansen , Michael Raymond Piacentino , Frederic William Brehm
发明人： Gooitzen Siemen van der Wal , Michael Wade Hansen , Michael Raymond Piacentino , Frederic William Brehm
IPC分类号： G06K940
CPC分类号： G06T1/20
摘要： A real-time modular video processing system (VPS) which can be scaled smoothly from relatively small systems with modest amounts of hardware to very large, very powerful systems with significantly more hardware. The modular video processing system includes a processing module containing at least one general purpose microprocessor which controls hardware and software operation of the video processing system using control data and which also facilitates communications with external devices. One or more video processing modules are also provided, each containing parallel pipelined video hardware which is programmable by the control data to provide different video processing operations on an input stream of video data. Each video processing module also contains one or more connections for accepting one or more daughterboards which each perform a particular image processing task. A global video bus routes video data between the processing module and each video processing module and between respective processing modules, while a global control bus provides the control data to/from the processing module from/to the video processing modules separate from the video data on the global video bus. A hardware control library loaded on the processing module provides an application programming interface including high level C-callable functions which allow programming of the video hardware as components are added and subtracted from the video processing system for different applications.
摘要翻译：一个实时的模块化视频处理系统（VPS），可以从具有适度数量的硬件的相对较小的系统平滑地扩展到具有更多硬件的非常大，非常强大的系统。模块化视频处理系统包括处理模块，该处理模块包含至少一个通用微处理器，其控制使用控制数据的视频处理系统的硬件和软件操作，并且还有助于与外部设备的通信。还提供一个或多个视频处理模块，每个视频处理模块包含并行流水线视频硬件，其可由控制数据编程，以对视频数据的输入流提供不同的视频处理操作。每个视频处理模块还包含用于接收一个或多个子板的一个或多个连接，每个子板执行特定的图像处理任务。全局视频总线在处理模块和每个视频处理模块之间以及各个处理模块之间路由视频数据，而全局控制总线从处理模块向/从与视频数据分开的视频处理模块提供控制数据全球视频总线。加载在处理模块上的硬件控制库提供了包括高级C可调用功能的应用程序编程接口，这些功能允许对视频硬件进行编程，作为从不同应用的视频处理系统添加和减少的组件。

3. 发明授权

US6151682A Digital signal processing circuitry having integrated timing information 有权
标题翻译：具有集成定时信息的数字信号处理电路
公开(公告)号：US6151682A
公开(公告)日：2000-11-21
申请号：US148661
申请日：1998-09-04
申请人： Gooitzen Siemen van der Wal , Michael Raymond Piacentino , Michael Wade Hansen
发明人： Gooitzen Siemen van der Wal , Michael Raymond Piacentino , Michael Wade Hansen
IPC分类号： G06F1/10 , G06F5/06 , G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00
CPC分类号： G06F5/06 , G06F1/10
摘要： Digital signal processing circuitry implemented in ASICs or FPGAs is built by combining multi-component constructs (e.g. macrocells). These circuits may be modified to include a timing channel by augmenting selected ones of the constructs to include a path which propagates a timing signal with a delay that compensates for the signal processing delay through the construct. The selected constructs are those that are used in a critical processing path in the digital signal processing circuitry. A timing compensation circuit may also be defined as a construct. This block receives two digital data signals having accompanying timing signals and delays the first signal that provides valid data until the second signal also provides valid data, as determined by their timing signals. A configurable arithmetic and logic unit (ALU) made using these techniques includes a timing compensation circuit, a look-up table and an accumulator. The configurable ALU may also include a timing signal selection circuit which selects between the each of two input timing signals, the logical AND of the input timing signals and the logical OR of the two input timing signals to produce an output timing signal. A programmable multiply-accumulator includes a matrix of multipliers, each of which may receive one of a plurality of input signals. The input signals are delayed through a pipeline and a portion of this pipeline is reserved for delaying one or more timing signals associated with the plurality of input signals. The delayed timing signals form the timing signals that are associated with the output signal of the programmable multiply accumulator.
摘要翻译：在ASIC或FPGA中实现的数字信号处理电路是通过组合多组分构造（例如，宏小区）构建的。这些电路可以被修改为包括定时信道，通过增加所选择的构造来包括传播具有补偿通过构造的信号处理延迟的延迟的定时信号的路径。所选择的构造是在数字信号处理电路中在关键处理路径中使用的结构。定时补偿电路也可以被定义为构造。该块接收具有附带的定时信号的两个数字数据信号，并延迟提供有效数据的第一信号，直到第二信号也提供由其定时信号确定的有效数据。使用这些技术制成的可配置的算术和逻辑单元（ALU）包括定时补偿电路，查找表和累加器。可配置ALU还可以包括定时信号选择电路，其在两个输入定时信号中的每一个之间选择输入定时信号的逻辑与和两个输入定时信号的逻辑或以产生输出定时信号。可编程乘法累加器包括乘法器矩阵，每个乘法器可以接收多个输入信号中的一个。输入信号通过流水线延迟，并且该流水线的一部分被保留用于延迟与多个输入信号相关联的一个或多个定时信号。延迟定时信号形成与可编程乘法累加器的输出信号相关联的定时信号。

4. 发明授权

US6061477A Quality image warper 失效
标题翻译：质量图像整形机
公开(公告)号：US6061477A
公开(公告)日：2000-05-09
申请号：US838101
申请日：1997-04-15
申请人： Mark S. Lohmeyer , Peter Jeffrey Burt , Gooitzen Siemen van der Wal
发明人： Mark S. Lohmeyer , Peter Jeffrey Burt , Gooitzen Siemen van der Wal
IPC分类号： H04N5/262 , G06T3/00 , G06T3/40 , H04N1/387 , G06K9/32
CPC分类号： G06T3/4007 , G06T3/4084
摘要： A digital image warper system produces a warped output image from an input image. The warper system increases the sampling rate of a sampled image above the Nyquist rate or samples an analog image at a higher rate than the Nyquist rate and prefilters the upsampled image to counteract filtering which may occur during the warping operation. The upsampled image is warped using an interpolator for resampling to produce a warped upsampled image. The interpolator is, for example, a low quality interpolator such as a bilinear interpolator. The warped image is then down-sampled to the same resolution as the input image to produce the warped image. Down-sampling and warping can be combined into one step by modifying the geometric transformation function implemented when warping the upsampled image.
摘要翻译：数字图像整经系统从输入图像产生翘曲输出图像。整经系统将采样图像的采样率提高到奈奎斯特速率以上，或以比奈奎斯特速率更高的速率采样模拟图像，并对上采样图像进行预滤波，以抵消在翘曲操作期间可能发生的滤波。上采样图像使用内插器进行扭曲以进行重采样以产生翘曲的上采样图像。内插器例如是诸如双线性内插器的低质量插值器。然后将翘曲的图像下采样到与输入图像相同的分辨率以产生翘曲图像。下采样和翘曲可以通过修改在对上采样图像进行翘曲时实现的几何变换函数而组合成一个步骤。

5. 发明授权

US5719966A Apparatus for assessing the visiblity of differences between two image sequences 失效
标题翻译：用于评估两个图像序列之间差异的可见性的装置
公开(公告)号：US5719966A
公开(公告)日：1998-02-17
申请号：US730275
申请日：1996-10-15
申请人： Michael Henry Brill , Gooitzen Siemen van der Wal , Jeffrey Lubin
发明人： Michael Henry Brill , Gooitzen Siemen van der Wal , Jeffrey Lubin
IPC分类号： G06T5/50 , H04N7/26 , H04N7/30 , G06T5/00 , G06T7/00
CPC分类号： G06T5/50 , H04N19/117 , H04N19/14 , H04N19/154 , H04N19/172 , H04N19/179 , H04N19/80 , H04N19/85 , H04N19/60
摘要： An apparatus for assessing the visibility of differences between two input image sequences. The apparatus comprises a pair of pre-filtered processors, a pair of pyramid constructors and a JND processor. Each pre-filter processor receives a separate input image sequence and performs temporal filtering to produce a low-pass temporal response and a bandpass temporal response. In turn, the pyramid constructors receive the temporal responses and generate contrast pyramids for the temporal responses. The JND processor evaluates the contrast pyramids to produce an image metric which is used to assess the visibility of differences between the two input image sequences.
摘要翻译：用于评估两个输入图像序列之间的差异的可见性的装置。该装置包括一对预过滤处理器，一对金字塔构造器和JND处理器。每个预滤波器处理器接收单独的输入图像序列并执行时间滤波以产生低通时间响应和带通时间响应。反过来，金字塔构造函数接收时间响应，并为时间响应生成对比金字塔。 JND处理器评估对比金字塔以产生用于评估两个输入图像序列之间的差异的可见性的图像度量。

6. 发明申请

US20050265633A1 Low latency pyramid processor for image processing systems 审中-公开
标题翻译：用于图像处理系统的低延迟金字塔处理器
公开(公告)号：US20050265633A1
公开(公告)日：2005-12-01
申请号：US11136908
申请日：2005-05-25
申请人： Michael Piacentino , Gooitzen Siemen van der Wal , Peter Burt , James Bergen
发明人： Michael Piacentino , Gooitzen Siemen van der Wal , Peter Burt , James Bergen
IPC分类号： G06K9/32 , G06K9/36 , G06K9/40 , G06K9/46 , G06T5/00 , G06T5/50
CPC分类号： G06T5/50 , G06T2207/20016 , G06T2207/20221
摘要： A video processor that uses a low latency pyramid processing technique for fusing images from multiple sensors. The imagery from multiple sensors is enhanced, warped into alignment, and then fused with one another in a manner that provides the fusing to occur within a single frame of video, i.e., sub-frame processing. Such sub-frame processing results in a sub-frame delay between a moment of capturing the images to the display of the fused imagery.
摘要翻译：一种视频处理器，使用低延迟金字塔处理技术来融合来自多个传感器的图像。来自多个传感器的图像被增强，扭曲成对齐，然后以提供融合发生在单个视频帧内，即子帧处理的方式彼此融合。这种子帧处理导致在将图像捕获到融合图像的显示之间的子帧延迟。

7. 发明授权

US06647150B2 Parallel pipeline processing system 失效
标题翻译：并行管道处理系统
公开(公告)号：US06647150B2
公开(公告)日：2003-11-11
申请号：US10272105
申请日：2002-10-16
申请人： Gooitzen Siemen van der Wal
发明人： Gooitzen Siemen van der Wal
IPC分类号： G06K940
CPC分类号： G06T1/20 , H04N19/17 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/537 , H04N19/59 , H04N19/80 , H04N19/85
摘要： A pipelined parallel processor (PPP) integrated circuit includes a filtering unit, internal routing circuitry such as a crosspoint switch, an internal frame store controller, and one or more function circuits. The function circuits include, for example, arithmetic units, lookup tables, timing compensators, adders/subtractors, statistics modules, image shifting circuitry, and other useful processing devices. The components of the PPP are interconnected with the crosspoint switch that routes data among the frame store controller, filtering unit, function circuits, external input channels, and external output channels. The internal frame store controller includes a plurality of programmable video line store memories that are coupled to an external field or frame store memory. Each line store memory may be programmed to provide data to, or receive data from one of the PPP components by a controller and to transfer the data from or to the memory, respectively. Access to the external memory by the line store memories is controlled by an arbitration processor which implements a priority scheme.
摘要翻译：流水线并行处理器（PPP）集成电路包括滤波单元，诸如交叉点开关的内部路由电路，内部帧存储控制器和一个或多个功能电路。功能电路包括例如运算单元，查找表，定时补偿器，加法器/减法器，统计模块，图像移位电路和其它有用的处理设备。 PPP的组件与交叉点交换机互连，交叉点交换机在帧存储控制器，滤波单元，功能电路，外部输入通道和外部输出通道之间路由数据。内部帧存储控制器包括耦合到外部场或帧存储器的多个可编程视频行存储存储器。每个行存储器可以被编程为分别向控制器提供数据或者从一个PPP组件接收数据，并分别将数据从存储器传送到存储器。通过线路存储器访问外部存储器由实现优先方案的仲裁处理器来控制。

8. 发明授权

US06567564B1 Pipelined pyramid processor for image processing systems 失效
标题翻译：用于图像处理系统的流水线金字塔处理器
公开(公告)号：US06567564B1
公开(公告)日：2003-05-20
申请号：US09411131
申请日：1999-10-04
申请人： Gooitzen Siemen van der Wal
发明人： Gooitzen Siemen van der Wal
IPC分类号： G06K940
CPC分类号： G06T1/20 , H04N19/17 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/537 , H04N19/59 , H04N19/80 , H04N19/85
摘要： A pipelined parallel processor (PPP) integrated circuit includes a filtering unit, internal routing circuitry such as a crosspoint switch, an internal frame store controller, and one or more function circuits. The function circuits include, for example, arithmetic units, lookup tables, timing compensators, adders/subtractors, statistics modules, image shifting circuitry, and other useful processing devices. The components of the PPP are interconnected with the crosspoint switch that routes data among the frame store controller, filtering unit, function circuits, external input channels, and external output channels. The internal frame store controller includes a plurality of programmable video line store memories that are coupled to an external field or frame store memory. Each line store memory may be programmed to provide data to, or receive data from one of the PPP components by a controller and to transfer the data from or to the memory, respectively. Access to the external memory by the line store memories is controlled by an arbitration processor which implements a priority scheme.
摘要翻译：流水线并行处理器（PPP）集成电路包括滤波单元，诸如交叉点开关的内部路由电路，内部帧存储控制器和一个或多个功能电路。功能电路包括例如运算单元，查找表，定时补偿器，加法器/减法器，统计模块，图像移位电路和其它有用的处理设备。 PPP的组件与交叉点交换机互连，交叉点交换机在帧存储控制器，滤波单元，功能电路，外部输入通道和外部输出通道之间路由数据。内部帧存储控制器包括耦合到外部场或帧存储器的多个可编程视频行存储存储器。每个线路存储器可以被编程为分别向控制器提供数据或从其中一个PPP组件接收数据，并分别将数据从存储器传送到存储器。通过线路存储器访问外部存储器由实现优先方案的仲裁处理器来控制。

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