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1. 发明授权

US07794510B1 On chip battery 有权
标题翻译：片上电池
公开(公告)号：US07794510B1
公开(公告)日：2010-09-14
申请号：US10988297
申请日：2004-11-12
申请人： Peter J. Hopper , William French , Robert Drury , Vladislav Vashchenko
发明人： Peter J. Hopper , William French , Robert Drury , Vladislav Vashchenko
IPC分类号： H01M10/04 , H01M4/64 , H01M2/20
CPC分类号： H01M10/42 , H01M2/361 , H01M10/0472 , H01M10/4257 , Y10T29/49108
摘要： In an on chip battery and method of making an on-chip battery, the electrodes are formed from metal layers deposited as part of the chip fabrication process. An electrolyte is preferably introduced between the electrodes at time of packaging of the chip.
摘要翻译：在片上电池和制造片上电池的方法中，电极由作为芯片制造工艺的一部分沉积的金属层形成。在芯片封装时，优选在电极之间引入电解质。

2. 发明授权

US07202538B1 Ultra low leakage MOSFET transistor 有权
标题翻译：超低漏电MOSFET晶体管
公开(公告)号：US07202538B1
公开(公告)日：2007-04-10
申请号：US10647604
申请日：2003-08-25
申请人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Robert Drury
发明人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Robert Drury
IPC分类号： H01L29/94
CPC分类号： H01L29/4238 , H01L21/28123 , H01L21/823481 , H01L21/823878 , H01L29/0692
摘要： A MOSFET transistor structure is formed in a substrate of semiconductor material having a first conductivity type. The MOSFET transistor structure includes an active region that is surrounded by a perimeter isolation dielectric material formed in the substrate to define a continuous sidewall interface between the sidewall dielectric material and the active region. Spaced-apart source and drain regions are formed in the active region and are also spaced-apart from the sidewall interface. A conductive gate electrode that is separated from the substrate channel region by intervening gate dielectric material includes a first portion that extends over the substrate channel region and a second portion that extends continuously over the entire sidewall interface between the isolation dielectric material and the active region. Thus, an enclosed ring is maintained around the entire composite perimeter, thereby completely avoiding regions of high trap density and, thus, preventing any current path for gate induced drain leakage (GIDL) to occur.
摘要翻译：在具有第一导电类型的半导体材料的衬底中形成MOSFET晶体管结构。 MOSFET晶体管结构包括由形成在衬底中的周边隔离电介质材料围绕以限定侧壁电介质材料和有源区域之间的连续侧壁界面的有源区域。间隔开的源极和漏极区域形成在有源区中并且也与侧壁界面间隔开。通过介入栅极电介质材料与衬底沟道区分离的导电栅电极包括在衬底沟道区上延伸的第一部分和在隔离电介质材料与有源区之间的整个侧壁界面上连续延伸的第二部分。因此，围绕整个复合材料周边保持封闭的环，从而完全避免高陷阱密度的区域，并因此防止发生栅极引起漏极泄漏（GIDL）的任何电流路径。

3. 发明授权

US06940133B1 Integrated trim structure utilizing dynamic doping 有权
标题翻译：采用动态掺杂的集成微调结构
公开(公告)号：US06940133B1
公开(公告)日：2005-09-06
申请号：US10818039
申请日：2004-04-05
申请人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Robert Drury
发明人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Robert Drury
IPC分类号： H01C17/26 , H01L21/02 , H01L29/76 , H01L29/8605 , H01L29/94
CPC分类号： H01L28/20 , H01C17/267 , H01L29/8605
摘要： An integrated circuit trim structure includes a dopant source, a target trim element formed in proximity to the dopant source, and a conductive heating element. The heater element is formed in proximity to the dopant source and includes first and second terminals and a trapezoid shaped region formed between the first and second terminals. As predefined current pulse is applied to the first terminal to promote current flow between the first and second terminals, a local heat source is created at a predefined location within the trapezoid shaped region and in proximity to the dopant source such that dopant flows from the dopant source into the target trim element to change the conductive characteristics of the target trim element.
摘要翻译：集成电路微调结构包括掺杂剂源，在掺杂剂源附近形成的目标微调元件和导电加热元件。加热器元件形成在掺杂剂源附近，并且包括形成在第一和第二端子之间的第一和第二端子和梯形区域。当预定义的电流脉冲施加到第一端子以促进第一和第二端子之间的电流流动时，在梯形区域内的预定位置处并且在掺杂剂源附近产生局部热源，使得掺杂剂从掺杂剂源到目标装饰元件以改变目标装饰元件的导电特性。

4. 发明授权

US07218555B2 Imaging cell that has a long integration period and method of operating the imaging cell 有权
标题翻译：成像细胞具有长的积分期和操作成像细胞的方法
公开(公告)号：US07218555B2
公开(公告)日：2007-05-15
申请号：US11242094
申请日：2005-10-03
申请人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Robert Drury
发明人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Robert Drury
IPC分类号： G11C11/34 , H01L29/788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11531 , H01L27/14603 , H01L27/14609
摘要： The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.
摘要翻译：成像单元的积分周期或成像单元暴露于光能的时间通过利用单聚电子可编程只读存储器（EPROM）结构捕获光能而大大增加。光能从EPROM结构的沟道区形成光电子。光生成的电子然后被加速成具有电离碰撞，其进而导致电子以与通道区域捕获的光子数成正比的速率注入到EPROM结构的浮动栅极上。

5. 发明授权

US06972457B1 Imaging cell that has a long integration period and method of operating the imaging cell 有权
标题翻译：成像细胞具有长的积分期和操作成像细胞的方法
公开(公告)号：US06972457B1
公开(公告)日：2005-12-06
申请号：US10821286
申请日：2004-04-09
申请人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Robert Drury
发明人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Robert Drury
IPC分类号： H01L21/8247 , H01L27/115 , H01L27/146 , H01L29/76 , H01L29/788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11531 , H01L27/14603 , H01L27/14609
摘要： The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.
摘要翻译：成像单元的积分周期或成像单元暴露于光能的时间通过利用单聚电子可编程只读存储器（EPROM）结构捕获光能而大大增加。光能从EPROM结构的沟道区形成光电子。光生成的电子然后被加速成具有电离碰撞，其进而导致电子以与通道区域捕获的光子数成正比的速率注入到EPROM结构的浮动栅极上。

6. 发明授权

US06852562B1 Low-cost method of forming a color imager 有权
标题翻译：低成本的彩色成像方法
公开(公告)号：US06852562B1
公开(公告)日：2005-02-08
申请号：US10728612
申请日：2003-12-05
申请人： Peter J. Hopper , Robert Drury , Philipp Lindorfer , Vladislav Vashchenko
发明人： Peter J. Hopper , Robert Drury , Philipp Lindorfer , Vladislav Vashchenko
IPC分类号： H01L21/00 , H01L27/146
CPC分类号： H01L27/14643 , H01L27/1462 , H01L27/14687
摘要： A color imager, which has a plurality of photodiodes, utilizes a layer of metal that is formed over the photodiodes. The metal layer has a plurality of different sized openings that lie vertically over the photodiodes to physically diffract, and thereby filter, the incident light that strikes the color imager.
摘要翻译：具有多个光电二极管的彩色成像器利用形成在光电二极管上的金属层。金属层具有多个不同尺寸的开口，其垂直地位于光电二极管上以物理衍射，从而过滤入射到彩色成像器的入射光。

7. 发明授权

US07005388B1 Method of forming through-the-wafer metal interconnect structures 有权
标题翻译：形成通过晶片的金属互连结构的方法
公开(公告)号：US07005388B1
公开(公告)日：2006-02-28
申请号：US10728319
申请日：2003-12-04
申请人： Peter J. Hopper , Vladislav Vashchenko , Peter Johnson , Robert Drury
发明人： Peter J. Hopper , Vladislav Vashchenko , Peter Johnson , Robert Drury
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05026 , H01L2224/05124 , H01L2224/05166 , H01L2224/05184 , H01L2224/0557 , H01L2224/05571 , H01L2224/05647 , H01L2224/13025 , H01L2224/131 , H01L2924/014 , H01L2924/00014
摘要： A semiconductor die is formed in a process that forms a hole through the wafer prior to the formation of the contacts and the metal-1 layer of an interconnect structure. The through-the-wafer hole is formed by using a wafer with a crystallographic orientation and a wet etch, such as with ethanol (KOH) or tetramethylammonium hydroxide (TMAH).
摘要翻译：在形成触点和互连结构的金属-1层之前，在形成穿过晶片的孔的工艺中形成半导体管芯。通过使用具有<110>结晶取向和湿蚀刻的晶片，例如用乙醇（KOH）或四甲基氢氧化铵（TMAH））形成贯通晶片孔。

8. 发明授权

US08878295B2 DMOS transistor with a slanted super junction drift structure 有权
标题翻译：具有倾斜超结漂移结构的DMOS晶体管
公开(公告)号：US08878295B2
公开(公告)日：2014-11-04
申请号：US13086187
申请日：2011-04-13
申请人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, Jr. , Punit Bhola , Vladislav Vashchenko
发明人： Peter J. Hopper , Alexei Sadovnikov , William French , Erika Mazotti , Richard Wendell Foote, Jr. , Punit Bhola , Vladislav Vashchenko
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/0882 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66659 , H01L29/66712 , H01L29/66734 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
摘要翻译：具有较低导通状态漏极至源极电阻和较高击穿电压的DMOS晶体管利用沿开口侧壁设置的倾斜超结漂移结构，漏极区位于开口底部和源极区靠近开口顶部。

9. 发明授权

US08524548B2 DMOS Transistor with a cavity that lies below the drift region 有权
标题翻译：具有位于漂移区下方的空腔的DMOS晶体管
公开(公告)号：US08524548B2
公开(公告)日：2013-09-03
申请号：US13094645
申请日：2011-04-26
申请人： William French , Vladislav Vashchenko , Richard Wendell Foote, Jr. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
发明人： William French , Vladislav Vashchenko , Richard Wendell Foote, Jr. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
IPC分类号： H01L29/66
CPC分类号： H01L29/7824 , H01L21/26586 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7835 , H01L29/78603
摘要： A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
摘要翻译：形成在绝缘体上硅（SOI）结构上的横向DMOS晶体具有较高的击穿电压，该击穿电压是由在SOI结构的体区形成的空穴产生的。空腔暴露SOI结构的绝缘体层的底部表面的一部分，其直接位于DMOS晶体管的漂移区的垂直下方。

10. 发明申请

US20120273881A1 DMOS Transistor with a Cavity that Lies Below the Drift Region 有权
标题翻译：具有位于漂移区下方的腔的DMOS晶体管
公开(公告)号：US20120273881A1
公开(公告)日：2012-11-01
申请号：US13094645
申请日：2011-04-26
申请人： William French , Vladislav Vashchenko , Richard Wendell Foote, JR. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
发明人： William French , Vladislav Vashchenko , Richard Wendell Foote, JR. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7824 , H01L21/26586 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7835 , H01L29/78603
摘要： A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
摘要翻译：形成在绝缘体上硅（SOI）结构上的横向DMOS晶体具有较高的击穿电压，该击穿电压是由在SOI结构的体区形成的空穴产生的。空腔暴露SOI结构的绝缘体层的底部表面的一部分，其直接位于DMOS晶体管的漂移区的垂直下方。

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