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1. 发明授权

US07274250B2 Low-voltage, buffered bandgap reference with selectable output voltage 有权
标题翻译：具有可选输出电压的低电压，缓冲带隙基准
公开(公告)号：US07274250B2
公开(公告)日：2007-09-25
申请号：US11170559
申请日：2005-06-28
申请人： Peter Hazucha , Sung T. Moon , Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Vivek De
发明人： Peter Hazucha , Sung T. Moon , Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Vivek De
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A temperature-independent voltage reference containing two independent bias circuits powered by the reference voltage, each bias circuit containing components with an exponential dependence of current on voltage and one containing a resistive impedance, and further including voltage dividers and an active component.
摘要翻译：独立于温度的电压基准包含由参考电压供电的两个独立偏置电路，每个偏置电路包含电流与电压的指数关系的分量，以及包含电阻阻抗的分量，并且还包括分压器和有源分量。

2. 发明申请

US20060290415A1 Low-voltage, buffered bandgap reference with selectable output voltage 有权
标题翻译：具有可选输出电压的低电压，缓冲带隙基准
公开(公告)号：US20060290415A1
公开(公告)日：2006-12-28
申请号：US11170559
申请日：2005-06-28
申请人： Peter Hazucha , Sung Moon , Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Vivek De
发明人： Peter Hazucha , Sung Moon , Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Vivek De
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A temperature-independent voltage reference containing two independent bias circuits powered by the reference voltage, each bias circuit containing components with an exponential dependence of current on voltage and one containing a resistive impedance, and further including voltage dividers and an active component.
摘要翻译：独立于温度的电压基准包含由参考电压供电的两个独立偏置电路，每个偏置电路包含电流与电压的指数关系的分量，以及包含电阻阻抗的分量，并且还包括分压器和有源分量。

3. 发明申请

US20050218972A1 Resonance suppression circuit 有权
标题翻译：谐振抑制电路
公开(公告)号：US20050218972A1
公开(公告)日：2005-10-06
申请号：US10813169
申请日：2004-03-31
申请人： Peter Hazucha , Jianping Xu , Gerhard Schrom , Tanay Karnik , Fabrice Paillet , Vivek De
发明人： Peter Hazucha , Jianping Xu , Gerhard Schrom , Tanay Karnik , Fabrice Paillet , Vivek De
IPC分类号： B23K9/00
CPC分类号： G06F1/305 , G06F1/28 , Y10T307/839
摘要： A resonance suppression circuit is provided to suppress resonance on a power grid of a chip or die. The resonance suppression circuit may include a band-pass filter portion, a comparator portion, an amplification portion and a current dissipation portion. The band-pass filter portion may include an inverter coupled between two signal lines of the power grid. The comparator portion may sense voltage fluctuations at approximately the resonance frequency and trigger the current dissipation portion to turn ON and thereby change the frequency spectrum of the load current on the power grid to suppress the power grid resonance.
摘要翻译：提供谐振抑制电路以抑制芯片或管芯的电网上的共振。谐振抑制电路可以包括带通滤波器部分，比较器部分，放大部分和电流消耗部分。带通滤波器部分可以包括耦合在电网的两个信号线之间的反相器。比较器部分可以感测大致谐振频率处的电压波动，并且触发电流耗散部分导通，从而改变电网上的负载电流的频谱以抑制电网谐振。

4. 发明申请

US20070013358A1 Multiphase transformer for a multiphase DC-DC converter 有权
标题翻译：多相DC-DC转换器的多相变压器
公开(公告)号：US20070013358A1
公开(公告)日：2007-01-18
申请号：US11173065
申请日：2005-06-30
申请人： Gerhard Schrom , Peter Hazucha , Jaeseo Lee , Fabrice Paillet , Tanay Karnik , Vivek De
发明人： Gerhard Schrom , Peter Hazucha , Jaeseo Lee , Fabrice Paillet , Tanay Karnik , Vivek De
IPC分类号： H01F30/12
CPC分类号： G05F1/468 , H02M1/14 , H02M7/068
摘要： A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
摘要翻译：提供了一种包括多相变压器的多相DC-DC转换器，多相变压器包括多个输入电压端子和变压器输出电压端子，每个输入电压端子与相应的相位相关联。将各相分配给多个输入电压端子的输入电压端子，以使多相变压器的输入电压端子处的纹波电流最小化。

5. 发明授权

US07504808B2 Multiphase transformer for a multiphase DC-DC converter 有权
标题翻译：多相DC-DC转换器的多相变压器
公开(公告)号：US07504808B2
公开(公告)日：2009-03-17
申请号：US11173065
申请日：2005-06-30
申请人： Gerhard Schrom , Peter Hazucha , Jaeseo Lee , Fabrice Paillet , Tanay Karnik , Vivek De
发明人： Gerhard Schrom , Peter Hazucha , Jaeseo Lee , Fabrice Paillet , Tanay Karnik , Vivek De
IPC分类号： G05F1/00
CPC分类号： G05F1/468 , H02M1/14 , H02M7/068
摘要： A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
摘要翻译：提供了一种包括多相变压器的多相DC-DC转换器，多相变压器包括多个输入电压端子和变压器输出电压端子，每个输入电压端子与相应的相位相关联。将各相分配给多个输入电压端子的输入电压端子，以使多相变压器的输入电压端子处的纹波电流最小化。

6. 发明授权

US08358112B2 Multiphase transformer for a multiphase DC-DC converter 有权
公开(公告)号：US08358112B2
公开(公告)日：2013-01-22
申请号：US12405136
申请日：2009-03-16
申请人： Gerhard Schrom , Peter Hazucha , Jaeseo Lee , Fabrice Paillet , Tanay Karnik , Vivek De
发明人： Gerhard Schrom , Peter Hazucha , Jaeseo Lee , Fabrice Paillet , Tanay Karnik , Vivek De
IPC分类号： G05F1/00
CPC分类号： G05F1/468 , H02M1/14 , H02M7/068
摘要： A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.

7. 发明申请

US20090174377A1 MULTIPHASE TRANSFORMER FOR A MULTIPHASE DC-DC CONVERTER 有权
标题翻译：用于多相DC-DC转换器的多相变压器
公开(公告)号：US20090174377A1
公开(公告)日：2009-07-09
申请号：US12405136
申请日：2009-03-16
申请人： Gerhard Schrom , Peter Hazucha , Jaeseo Lee , Fabrice Paillet , Tanay Karnik , Vivek De
发明人： Gerhard Schrom , Peter Hazucha , Jaeseo Lee , Fabrice Paillet , Tanay Karnik , Vivek De
IPC分类号： G05F1/00
CPC分类号： G05F1/468 , H02M1/14 , H02M7/068
摘要： A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
摘要翻译：提供了一种包括多相变压器的多相DC-DC转换器，多相变压器包括多个输入电压端子和变压器输出电压端子，每个输入电压端子与相应的相位相关联。将各相分配给多个输入电压端子的输入电压端子，以使多相变压器的输入电压端子处的纹波电流最小化。

8. 发明授权

US07394298B2 Stepwise drivers for DC/DC converters 有权
标题翻译： DC / DC转换器的逐步驱动
公开(公告)号：US07394298B2
公开(公告)日：2008-07-01
申请号：US10919672
申请日：2004-08-16
申请人： Peter Hazucha , Sung T. Moon , Gerhard Schrom , Tanay Karnik , Vivek De
发明人： Peter Hazucha , Sung T. Moon , Gerhard Schrom , Tanay Karnik , Vivek De
IPC分类号： H03K3/00
CPC分类号： H02M1/08 , H03K4/023
摘要： Stepwise drivers for DC/DC converters are described herein. In one embodiment, a stepwise driver is provided to charge or discharge a gate capacitance of a power switch of a DC/DC converter. In a particular embodiment, a stepwise driver example includes multiple switching elements to sequentially switch to charge a gate capacitance of a power switch of a DC/DC converter from a first voltage to a second voltage in multiple steps. Other methods and apparatuses are also described.
摘要翻译：本文描述了用于DC / DC转换器的逐步驱动器。在一个实施例中，提供逐步驱动器以对DC / DC转换器的电源开关的栅极电容进行充电或放电。在特定实施例中，逐步驱动器示例包括多个开关元件，以顺序切换以将DC / DC转换器的电源开关的栅极电容从多个步骤中的第一电压从第一电压充电到第二电压。还描述了其它方法和装置。

9. 发明申请

US20060291265A1 Memory cell driver circuits 有权
标题翻译：存储单元驱动电路
公开(公告)号：US20060291265A1
公开(公告)日：2006-12-28
申请号：US11169106
申请日：2005-06-27
申请人： Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Dinesh Somasekhar , Yibin Ye , Ali Keshavarzi , Muhammad Khellah , Vivek De
发明人： Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Dinesh Somasekhar , Yibin Ye , Ali Keshavarzi , Muhammad Khellah , Vivek De
IPC分类号： G11C17/00
CPC分类号： G11C17/18
摘要： A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.
摘要翻译：系统包括用于对存储器单元进行编程的上拉电路。上拉电路可以包括电平移位器以接收控制信号，电源电压以及多个轨道电压中的一个或多个，多个轨道电压中的每一个基本上等于电源电压的相应整数倍，并产生第二控制信号和共源共栅级。共源共栅级可以包括多个晶体管，多个晶体管中的每一个的栅极电压至少部分地由第二控制信号，电源电压和多个轨道中的至少一个轨道电压和输出节点以提供单元编程信号。

10. 发明授权

US07030676B2 Timing circuit for separate positive and negative edge placement in a switching DC-DC converter 失效
标题翻译：用于在开关DC-DC转换器中单独的正和负边缘放置的定时电路
公开(公告)号：US07030676B2
公开(公告)日：2006-04-18
申请号：US10748298
申请日：2003-12-31
申请人： Peter Hazucha , Gerhard Schrom , Tanay Karnik , Vivek De
发明人： Peter Hazucha , Gerhard Schrom , Tanay Karnik , Vivek De
IPC分类号： H03H11/26
CPC分类号： H03K5/135 , H02M3/157
摘要： A timing circuit independently controls placement of the positive and negative edges of a periodic signal. This signal may then be used to control a wide variety of integrated circuit applications. The timing circuit includes separate programmable delay lines and a signal processor. Each delay line delays an input clock signal by a different increment of time. The signal processor then generates a timing signal from the clock signal, where the timing signal has a first edge controlled by the first delayed clock signal and a second edge controlled by the second delayed clock signal. The edges may be controlled so that the timing signal assumes different logical values for different amounts of time, thereby customizing the signal to any application. An example of one application includes using the timing signal control switching in a DC-DC converter.
摘要翻译：定时电路独立地控制周期信号的正和负边缘的放置。然后可以将该信号用于控制各种各样的集成电路应用。定时电路包括单独的可编程延迟线和信号处理器。每个延迟线将输入时钟信号延迟不同的时间增量。信号处理器随后从时钟信号产生定时信号，其中定时信号具有由第一延迟时钟信号控制的第一边沿和由第二延迟时钟信号控制的第二边沿。可以控制边缘使得定时信号在不同的时间量内采用不同的逻辑值，从而将信号定制到任何应用。一个应用的示例包括在DC-DC转换器中使用定时信号控制切换。

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