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1. 发明授权

US07378331B2 Methods of vertically stacking wafers using porous silicon 有权
标题翻译：使用多孔硅垂直堆叠晶圆的方法
公开(公告)号：US07378331B2
公开(公告)日：2008-05-27
申请号：US11025131
申请日：2004-12-29
申请人： Mohamad Shaheen , Peter G. Tolchinsky , Irwin Yablok , Scott R. List
发明人： Mohamad Shaheen , Peter G. Tolchinsky , Irwin Yablok , Scott R. List
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L24/81 , H01L21/6835 , H01L21/76259 , H01L25/0657 , H01L25/50 , H01L2224/81001 , H01L2224/81801 , H01L2924/01033 , H01L2924/14
摘要： A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.
摘要翻译：一种提供三维（3-D）IC晶片工艺流程的方法和制品。在一些实施例中，所述方法和制品包括将多层晶片的器件层接合到另一多层晶片的器件层以形成键合的器件层对，所述多层晶片中的每一个在多孔硅层上包括硅层（SiOPSi），其中所述器件层形成在所述硅层中，通过分离所述多孔硅层之一将所述一对器件层与所述硅衬底中的一个分离，并且将所述一对器件层与所述多个硅层分离通过分离另一个多孔硅层来提供剩余的硅衬底以提供垂直堆叠的晶片。

2. 发明申请

US20090096025A1 Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer 审中-公开
标题翻译：用于制造具有蚀刻停止层的绝缘体上硅（SOI）晶片的方法
公开(公告)号：US20090096025A1
公开(公告)日：2009-04-16
申请号：US12316737
申请日：2008-12-15
申请人： Peter G. Tolchinsky , Martin D. Giles , Michael L. McSwiney , Mohamad Shaheen , Irwin Yablok
发明人： Peter G. Tolchinsky , Martin D. Giles , Michael L. McSwiney , Mohamad Shaheen , Irwin Yablok
IPC分类号： H01L27/00
CPC分类号： H01L21/26533 , H01L21/76243
摘要： Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.
摘要翻译：公开了具有覆盖掩埋氧化物层的蚀刻停止层的绝缘体上硅（SOI）晶片的实施例以及其制造方法的实施例。蚀刻停止层可以包括氮化硅，氮掺杂二氧化硅或氮氧化硅，以及这些材料的某些组合。描述和要求保护其他实施例。

3. 发明授权

US07491988B2 Transistors with increased mobility in the channel zone and method of fabrication 有权
标题翻译：晶体管在沟道区域的迁移率增加和制造方法
公开(公告)号：US07491988B2
公开(公告)日：2009-02-17
申请号：US10880311
申请日：2004-06-28
申请人： Peter G. Tolchinsky , Mark Bohr , Irwin Yablok
发明人： Peter G. Tolchinsky , Mark Bohr , Irwin Yablok
IPC分类号： H01L29/72
CPC分类号： H01L29/1054 , H01L29/517 , H01L29/66651 , H01L29/66795 , H01L29/785 , H01L29/78687
摘要： A semiconductor transistor structure with increased mobility in the channel zone and a method of its fabrication are described. A semiconductor substrate having a first dopant is formed. A diffusion barrier layer having a second dopant is formed on the semiconductor substrate to suppress outdiffusion of the first dopant. Next, a semiconductor layer having substantially low dopant concentration relative to the first layer is epitaxially grown on the diffusion barrier layer. The semiconductor layer defines a channel in the semiconductor transistor structure. The low dopant concentration in the semiconductor layer increases the mobility of the carriers in the channel of the semiconductor transistor structure. A gate electrode and a gate dielectric are formed on the semiconductor layer with the low dopant concentration.
摘要翻译：描述了在沟道区中具有增加的迁移率的半导体晶体管结构及其制造方法。形成具有第一掺杂剂的半导体衬底。在半导体衬底上形成具有第二掺杂剂的扩散阻挡层，以抑制第一掺杂剂的扩散。接下来，在扩散阻挡层上外延生长相对于第一层具有相当低的掺杂剂浓度的半导体层。半导体层限定半导体晶体管结构中的沟道。半导体层中的低掺杂剂浓度增加了半导体晶体管结构的沟道中载流子的迁移率。在低掺杂浓度的半导体层上形成栅极电极和栅极电介质。

4. 发明授权

US07473614B2 Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer 失效
公开(公告)号：US07473614B2
公开(公告)日：2009-01-06
申请号：US10987775
申请日：2004-11-12
申请人： Peter G. Tolchinsky , Martin D. Giles , Michael L. McSwiney , Mohamad Shaheen , Irwin Yablok
发明人： Peter G. Tolchinsky , Martin D. Giles , Michael L. McSwiney , Mohamad Shaheen , Irwin Yablok
IPC分类号： H01L21/76
CPC分类号： H01L21/26533 , H01L21/76243
摘要： Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.

5. 发明授权

US06924543B2 Method for making a semiconductor device having increased carrier mobility 有权
标题翻译：制造具有增加的载流子迁移率的半导体器件的方法
公开(公告)号：US06924543B2
公开(公告)日：2005-08-02
申请号：US10463766
申请日：2003-06-16
申请人： Peter G. Tolchinsky , Irwin Yablok
发明人： Peter G. Tolchinsky , Irwin Yablok
IPC分类号： H01L21/762 , H01L21/8234 , H01L29/72
CPC分类号： H01L29/7842 , H01L21/76232 , H01L21/823412 , H01L21/823481
摘要： A method and apparatus for a semiconductor device having increased electrical carrier mobility is described. That method and apparatus comprises forming two recesses within a substrate, and providing a material within the two recesses. The material has a predetermined coefficient of thermal expansion (CTE) to facilitate introduction of a predetermined strain within the substrate in a location between the two recesses. Also described is a semiconductor device that comprises a substrate having two recesses formed therein, and a material disposed within the two recesses. The material has a predetermined coefficient of thermal expansion (CTE) to facilitate introduction of a predetermined strain within the substrate in a location between the two recesses.
摘要翻译：描述了具有增加的电载流子迁移率的半导体器件的方法和装置。该方法和设备包括在基底内形成两个凹槽，并在两个凹槽内提供材料。该材料具有预定的热膨胀系数（CTE），以便于在两个凹部之间的位置中将衬底内的预定应变引入。还描述了一种半导体器件，其包括其中形成有两个凹部的衬底和设置在两个凹部内的材料。该材料具有预定的热膨胀系数（CTE），以便于在两个凹部之间的位置中将衬底内的预定应变引入。

6. 发明申请

US20100155880A1 Back gate doping for SOI substrates 审中-公开
标题翻译： SOI衬底的背栅掺杂
公开(公告)号：US20100155880A1
公开(公告)日：2010-06-24
申请号：US12317449
申请日：2008-12-23
申请人： Ibrahim Ban , Peter G. Tolchinsky , Irwin Yablok
发明人： Ibrahim Ban , Peter G. Tolchinsky , Irwin Yablok
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/76254 , H01L29/7841 , H01L29/78648
摘要： A silicon-on-insulator (SOI) substrate comprises a base silicon substrate having a back gate region, wherein the back gate region has a first dopant concentration that is greater than 1×1017 cm−3, a nitrogen layer adjacent to the back gate region of the base silicon substrate, a BOX layer adjacent to the nitrogen layer, and a thin silicon device layer adjacent to the BOX layer, wherein the thin silicon device layer has a first dopant concentration that is less than 1×1017 cm−3. In some implementations, the thin silicon device layer has a first dopant concentration that is less than 1×1015 cm−3.
摘要翻译：绝缘体上硅（SOI）衬底包括具有背栅区的基硅衬底，其中所述背栅区具有大于1×1017cm-3的第一掺杂浓度，与所述背栅相邻的氮层基底硅衬底的区域，与氮层相邻的BOX层以及与BOX层相邻的薄硅器件层，其中所述薄硅器件层具有小于1×1017cm-3的第一掺杂剂浓度。在一些实施方案中，薄硅器件层具有小于1×1015cm-3的第一掺杂剂浓度。

7. 发明授权

US06911380B2 Method of forming silicon on insulator wafers 失效
标题翻译：在绝缘体晶圆上形成硅的方法
公开(公告)号：US06911380B2
公开(公告)日：2005-06-28
申请号：US10199123
申请日：2002-07-22
申请人： Peter G. Tolchinsky , Irwin Yablok , Mohamad A. Shaheen
发明人： Peter G. Tolchinsky , Irwin Yablok , Mohamad A. Shaheen
IPC分类号： H01L21/762 , H01L21/44
CPC分类号： H01L21/76254 , H01L21/76243 , H01L21/76256 , H01L21/76262
摘要： A method is provided for fabricating an SOI water. This may involve forming a silicon substrate and implanting oxygen into the substrate. Damaged portions of the implanted silicon may be healed/cured by CMP or anneal, for example. An epi layer may then be deposited over the healed/cured regions of the substrate. The substrate may then be annealed to form an insulative layer. The wafer may be thinned to provide the proper thickness of the epi layer.
摘要翻译：提供了制造SOI水的方法。这可能涉及形成硅衬底并将氧注入到衬底中。植入的硅的损伤部分可以例如通过CMP来愈合/固化或退火。然后可以将epi层沉积在衬底的愈合/固化区域上。然后可以将衬底退火以形成绝缘层。可以使晶片变薄以提供外延层的适当厚度。

8. 发明授权

US08143646B2 Stacking fault and twin blocking barrier for integrating III-V on Si 有权
标题翻译：堆叠故障和双阻挡屏障，用于在Si上集成III-V
公开(公告)号：US08143646B2
公开(公告)日：2012-03-27
申请号：US11498901
申请日：2006-08-02
申请人： Mantu K. Hudait , Mohamad A. Shaheen , Loren A. Chow , Peter G. Tolchinsky , Joel M. Fastenau , Dmitri Loubychev , Amy W. K. Liu
发明人： Mantu K. Hudait , Mohamad A. Shaheen , Loren A. Chow , Peter G. Tolchinsky , Joel M. Fastenau , Dmitri Loubychev , Amy W. K. Liu
IPC分类号： H01L21/02
CPC分类号： H01L29/7785 , H01L21/02381 , H01L21/02433 , H01L21/02466 , H01L21/02549 , H01L21/02617 , H01L29/66462
摘要： A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.
摘要翻译：描述了在硅衬底上形成III-V器件层的层叠故障和双阻挡屏障及其制造方法。本发明的实施方案能够在硅衬底上形成缺陷密度低于1×10 8 cm -2的III-V InSb器件层。在本发明的实施例中，缓冲层位于III-V器件层和硅衬底之间以滑动位错。在本发明的一个实施例中，基于晶格常数，带隙和熔点选择GaSb缓冲层，以防止许多晶格缺陷从缓冲器传播到III-V器件层中。在具体实施例中，III-V InSb器件层直接形成在GaSb缓冲器上。

9. 发明申请

US20100327261A1 HIGH HOLE MOBILITY P-CHANNEL GE TRANSISTOR STRUCTURE ON SI SUBSTRATE 有权
标题翻译：基板上的高孔移动通道晶体管结构
公开(公告)号：US20100327261A1
公开(公告)日：2010-12-30
申请号：US12876922
申请日：2010-09-07
申请人： Mantu K. Hudait , Suman Datta , Jack T. Kavalieros , Peter G. Tolchinsky
发明人： Mantu K. Hudait , Suman Datta , Jack T. Kavalieros , Peter G. Tolchinsky
IPC分类号： H01L29/775 , H01L29/20
CPC分类号： H01L29/7782 , H01L21/02381 , H01L21/02433 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/02573 , H01L21/0262 , H01L29/267 , H01L29/66431
摘要： The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种在硅（“Si”）衬底上实现高空穴迁移率p沟道锗（“Ge”）晶体管结构的装置和方法。一个示例性装置可以包括包括GaAs成核层，第一GaAs缓冲层和第二GaAs缓冲层的缓冲层。该示例性装置还可以包括第二GaAs缓冲层上的底部阻挡层，并具有大于1.1eV的带隙，底部势垒上的Ge活性通道层，并且相对于底部势垒的价带偏移大于0.3 eV和Ge活性通道层上的AlAs顶部势垒，其中AlAs顶部势垒具有大于1.1eV的带隙。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

10. 发明授权

US09711591B2 Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby 有权
公开(公告)号：US09711591B2
公开(公告)日：2017-07-18
申请号：US13997607
申请日：2011-12-28
申请人： Niloy Mukherjee , Matthew V. Metz , James M. Powers , Van H. Le , Benjamin Chu-Kung , Mark R. Lemay , Marko Radosavljevic , Niti Goel , Loren Chow , Peter G. Tolchinsky , Jack T. Kavalieros , Robert S. Chau
发明人： Niloy Mukherjee , Matthew V. Metz , James M. Powers , Van H. Le , Benjamin Chu-Kung , Mark R. Lemay , Marko Radosavljevic , Niti Goel , Loren Chow , Peter G. Tolchinsky , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/02 , H01L29/06
CPC分类号： H01L29/06 , H01L21/0237 , H01L21/0245 , H01L21/02455 , H01L21/02494 , H01L21/02502 , H01L21/02505 , H01L21/0251 , H01L21/02513 , H01L21/02532 , H01L21/02538 , H01L21/02587 , H01L21/0259 , H01L21/02617 , H01L21/02636 , H01L21/02658 , H01L21/02664
摘要： Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

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