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1. 发明授权

US5519193A Method and apparatus for stressing, burning in and reducing leakage current of electronic devices using microwave radiation 失效
标题翻译：使用微波辐射强化，燃烧和减少电子设备泄漏电流的方法和装置
公开(公告)号：US5519193A
公开(公告)日：1996-05-21
申请号：US966960
申请日：1992-10-27
申请人： Peter E. Freiermuth , Kathleen S. Ginn , Jeffrey A. Haley , Susan J. Lamaire , David A. Lewis , Gavin T. Mills , Timothy A. Redmond , Yuk L. Tsang , Joseph J. Van Horn , Alfred Viehbeck , George F. Walker , Jer-Ming Yang , Clarence S. Long
发明人： Peter E. Freiermuth , Kathleen S. Ginn , Jeffrey A. Haley , Susan J. Lamaire , David A. Lewis , Gavin T. Mills , Timothy A. Redmond , Yuk L. Tsang , Joseph J. Van Horn , Alfred Viehbeck , George F. Walker , Jer-Ming Yang , Clarence S. Long
IPC分类号： G01R31/26 , G01R31/28 , G01R31/311 , H01L21/265 , H01L21/268 , H01L21/326 , H01L21/329 , H05B6/80
CPC分类号： G01R31/2881 , G01R31/311 , Y10S148/071
摘要： The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging substrates and the combination of a semiconductor chip mounted onto a semiconductor chip packaging substrate. Microwaves burn-in devices in a substantially shorter period of time than conventional burn-in techniques and avoid the need for special workpiece holders which are required by conventional stress and burn-in techniques. Additionally, microwave methods are described for reducing the leakage current of recitfying junctions, such as PN junctions and Schottky barrier diode junctions of semiconductor devices on fully processed semiconductor chips and wafers.
摘要翻译：所描述的发明涉及在半导体芯片单独和晶圆级别的烧结，电应力，热应力和减少整流结漏电流的微波方法，以及对半导体芯片封装衬底的燃烧和应力的组合安装在半导体芯片封装基板上的半导体芯片。微波老化装置在比传统的老化技术更短的时间内，并且避免了对于常规应力和老化技术所要求的特殊工件支架的需要。此外，描述了微波方法，用于减少重新连接的漏电流，例如半导体器件在完全处理的半导体芯片和晶片上的PN结和肖特基势垒二极管接头。

2. 发明授权

US4888297A Process for making a contact structure including polysilicon and metal alloys 失效
标题翻译：制造包括多晶硅和金属合金的接触结构的方法
公开(公告)号：US4888297A
公开(公告)日：1989-12-19
申请号：US110996
申请日：1987-10-20
申请人： Mohamed O. Aboelfotoh , Yuk L. Tsang
发明人： Mohamed O. Aboelfotoh , Yuk L. Tsang
IPC分类号： H01L21/285 , H01L23/485
CPC分类号： H01L21/28525 , H01L23/485 , H01L2924/0002 , Y10S148/02
摘要： A multi-layer contact process is described for providing contact to a shallow semiconductor region forming a semiconductor PN junction and with a silicon semiconductor body. The multi-layer structure includes a layer of polycrystalline silicon doped with an impurity of the same conductivity type as that of the semiconductor region. A first layer of a refractory alloy is deposited over the polycrystalline silicon layer to provide electrically stable interface therewith. A second layer of another refractory metal or alloy is deposited over the first refractory metal alloy layer and serves to protect the shallow PN junction against current leakage failure. A third layer of interconnect metal is deposited over the multi-layer contact structure. The resulting structure provides a low resistance ohmic contact to a shallow semiconductor region with improved electrical characteristics.
摘要翻译：描述了用于提供与形成半导体PN结的浅半导体区域和硅半导体本体的接触的多层接触工艺。多层结构包括掺杂有与半导体区域相同导电类型的杂质的多晶硅层。难熔合金的第一层沉积在多晶硅层上以提供与其电气稳定的界面。第二层另一难熔金属或合金沉积在第一难熔金属合金层上，用于保护浅PN结免受电流泄漏故障。第三层互连金属沉积在多层接触结构上。所得结构为具有改善的电特性的浅半导体区域提供低电阻欧姆接触。

3. 发明授权

US07651939B2 Method of blocking a void during contact formation 有权
标题翻译：在接触形成期间堵塞空隙的方法
公开(公告)号：US07651939B2
公开(公告)日：2010-01-26
申请号：US11742942
申请日：2007-05-01
申请人： Yuk L. Tsang
发明人： Yuk L. Tsang
IPC分类号： H01L21/4763
CPC分类号： H01L23/485 , H01L21/7682 , H01L21/76831 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： An electronic device can include conductive regions. A void can extend between different portions of an insulating layer. Different openings can intersect the void. A liner layer can substantially block the void, substantially preventing subsequently forming an electrical leakage path along the void. In one aspect, a stressor layer can be deposited over the conductive regions prior to forming the insulating layer. The liner layer can be formed over the stressor layer within the different openings through the insulating layer. In another aspect, an etch-stop layer can be formed over a silicide layer prior to forming the insulating layer. After removing a portion of the liner layer, a portion of the etch-stop layer can be removed to expose the silicide layer within the different openings. In yet another aspect, a nitride layer can lie between a substrate and the insulating layer and include a section of the openings.
摘要翻译：电子设备可以包括导电区域。空隙可以在绝缘层的不同部分之间延伸。不同的开口可以与空隙相交。内衬层可以基本上阻挡空隙，基本上防止随后形成沿着空隙的漏电路径。在一个方面，在形成绝缘层之前，应力层可以沉积在导电区域上。可以通过绝缘层在不同开口内的应力层上形成衬垫层。在另一方面，在形成绝缘层之前，可以在硅化物层之上形成蚀刻停止层。在去除衬里层的一部分之后，可以去除蚀刻停止层的一部分以露出不同开口内的硅化物层。在另一方面，氮化物层可以位于衬底和绝缘层之间，并且包括开口的一部分。

4. 发明申请

US20080272492A1 METHOD OF BLOCKING A VOID DURING CONTACT FORMATION PROCESS AND DEVICE HAVING THE SAME 有权
标题翻译：在接触形成过程中堵塞空气的方法和具有该空穴的装置
公开(公告)号：US20080272492A1
公开(公告)日：2008-11-06
申请号：US11742942
申请日：2007-05-01
申请人： Yuk L. Tsang
发明人： Yuk L. Tsang
IPC分类号： H01L23/528 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/7682 , H01L21/76831 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： An electronic device can include conductive regions. A void can extend between different portions of an insulating layer. Different openings can intersect the void. A liner layer can substantially block the void, substantially preventing subsequently forming an electrical leakage path along the void. In one aspect, a stressor layer can be deposited over the conductive regions prior to forming the insulating layer. The liner layer can be formed over the stressor layer within the different openings through the insulating layer. In another aspect, an etch-stop layer can be formed over a silicide layer prior to forming the insulating layer. After removing a portion of the liner layer, a portion of the etch-stop layer can be removed to expose the silicide layer within the different openings. In yet another aspect, a nitride layer can lie between a substrate and the insulating layer and include a section of the openings.
摘要翻译：电子设备可以包括导电区域。空隙可以在绝缘层的不同部分之间延伸。不同的开口可以与空隙相交。内衬层可以基本上阻挡空隙，基本上防止随后形成沿着空隙的漏电路径。在一个方面，在形成绝缘层之前，应力层可以沉积在导电区域上。可以通过绝缘层在不同开口内的应力层上形成衬垫层。在另一方面，在形成绝缘层之前，可以在硅化物层之上形成蚀刻停止层。在去除衬里层的一部分之后，可以去除蚀刻停止层的一部分以露出不同开口内的硅化物层。在另一方面，氮化物层可以位于衬底和绝缘层之间，并且包括开口的一部分。

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