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1. 发明申请

US20070200173A1 Embedded substrate interconnect for underside contact to source and drain regions 有权
标题翻译：用于下侧接触源极和漏极区域的嵌入式衬底互连
公开(公告)号：US20070200173A1
公开(公告)日：2007-08-30
申请号：US11356229
申请日：2006-02-16
申请人： Perry Pelley , Troy Cooper , Michael Mendicino
发明人： Perry Pelley , Troy Cooper , Michael Mendicino
IPC分类号： H01L27/12
CPC分类号： H01L29/41733 , H01L21/84 , H01L27/12
摘要： A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) arranged above a wafer substrate (12) and forming a silicon layer (24) upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate (28) upon an SOI substrate having a conductive line (16) embedded therein and implanting dopants within the semiconductor topography to form source and drain regions (30) within an upper semiconductor layer (24) of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.
摘要翻译：提供一种半导体图形（10），其包括绝缘体上半导体（SOI）基板，其具有布置在SOI衬底的绝缘层（22）内的导线（16）。一种用于形成具有这种结构的SOI衬底的方法包括在布置在晶片衬底（12）上方的绝缘层（22）内形成第一导电线（16），并在第一导线的表面上形成硅层（24）和绝缘层。提供了一种另外的方法，其包括在SOI衬底上形成晶体管栅极（28），该SOI衬底具有嵌入其中的导电线（16），并且在半导体拓扑图内注入掺杂剂以在上半导体层内形成源区和漏区（30）（24），使得源极和漏极区域之一的下侧与导电线接触。

2. 发明申请

US20070237021A1 Memory with clocked sense amplifier 有权
标题翻译：内置时钟读出放大器
公开(公告)号：US20070237021A1
公开(公告)日：2007-10-11
申请号：US11392402
申请日：2006-03-29
申请人： Perry Pelley
发明人： Perry Pelley
IPC分类号： G11C8/00
CPC分类号： G11C7/08 , G11C7/22 , G11C7/222 , G11C11/419
摘要： In one form a memory and method thereof has a memory array having a plurality of columns of bit lines and a plurality of intersecting rows of word lines. Control circuitry is coupled to the memory array for successively accessing predetermined bit locations in the memory array during successive memory cycles. The control circuitry senses data within the memory array at a beginning of a predetermined memory cycle. Timing of the memory cycle is determined from a single external clock edge of a memory system clock. During a single memory cycle the memory initially performs the function of sensing followed by at least the functions of precharging the bit lines, addressing and developing a signal to be sensed. In one form each of the successive memory cycles is a period of time of no more than a single period of the memory system clock.
摘要翻译：在一种形式中，其存储器及其方法具有存储器阵列，该存储器阵列具有多列位线和多条相交行的字线。控制电路耦合到存储器阵列，用于在连续存储器周期期间连续访问存储器阵列中的预定位位置。控制电路在预定存储器周期的开始处感测存储器阵列内的数据。存储器周期的定时由存储器系统时钟的单个外部时钟边缘确定。在单个存储器循环期间，存储器最初执行感测功能，至少至少是对位线进行预充电，寻址和显影要被感测的信号的功能。在一种形式中，每个连续存储器周期是不超过存储器系统时钟的单个周期的时间段。

3. 发明申请

US20050122198A1 Inductive device including bond wires 有权
标题翻译：感应装置包括接合线
公开(公告)号：US20050122198A1
公开(公告)日：2005-06-09
申请号：US10729531
申请日：2003-12-05
申请人： Yaping Zhou , Susan Downey , Sheila Chopin , Tu-Anh Tran , Alan Woosley , Peter Harper , Perry Pelley
发明人： Yaping Zhou , Susan Downey , Sheila Chopin , Tu-Anh Tran , Alan Woosley , Peter Harper , Perry Pelley
IPC分类号： H01F17/00 , H01F41/04 , H01L23/522 , H01F5/00
CPC分类号： H01F17/0033 , H01F41/046 , H01L23/5227 , H01L23/645 , H01L24/45 , H01L24/48 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4813 , H01L2924/00014 , H01L2924/01079 , H01L2924/09701 , H01L2924/14 , H01L2924/30107 , H01L2924/3025 , Y10T29/4902 , H01L2224/45015 , H01L2924/207
摘要： An inductive device (105) is formed above a substrate (225) having a conductive coil formed around a core (109). The coil comprises segments formed from a first plurality of bond wires (113) and a second plurality of bond wires (111). The first plurality of bond wires (113) extends between the core (109) and the substrate (225). Each of the first plurality of bond wires is coupled to two of a plurality of wire bond pads (117, 116). The second plurality of bond wires (111) extends over the core (109) and is coupled between two of the plurality of wire bond pads (117, 119). A shield (141) includes a portion that is positioned between the core (109) and the substrate (225).
摘要翻译：在具有围绕芯（109）形成的导电线圈的衬底（225）上方形成感应器件（105）。线圈包括由第一多个接合线（113）和第二多个接合线（111）形成的线段。第一多个接合线（113）在芯（109）和衬底（225）之间延伸。第一多个接合线中的每一个耦合到多个引线接合焊盘（117,116）中的两个。所述第二多个接合线（111）在所述芯（109）上方延伸并耦合在所述多个引线接合焊盘（117,119）中的两个之间。屏蔽（141）包括位于芯（109）和衬底（225）之间的部分。

4. 发明申请

US20060010350A1 Memory having variable refresh control and method therefor 有权
标题翻译：具有可变刷新控制的存储器及其方法
公开(公告)号：US20060010350A1
公开(公告)日：2006-01-12
申请号：US10886340
申请日：2004-07-07
申请人： Perry Pelley , John Burgan
发明人： Perry Pelley , John Burgan
IPC分类号： G06F11/00
CPC分类号： G11C11/406 , G11C7/04 , G11C11/401 , G11C11/40615 , G11C11/40626 , G11C29/006 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2211/4061
摘要： A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.
摘要翻译：存储器（10）具有存储器阵列（12），电荷泵（18），电压调节器（20），刷新控制电路（16）和刷新计数器（22）。电荷泵（18）向存储器阵列（12）提供衬底偏置。电压调节器（20）提供泵使能信号，用于将衬底偏置的电压电平维持在上限和下限内。刷新控制电路（16）控制刷新操作。刷新计数器（22）被耦合以接收泵使能信号，并且作为响应，向刷新控制电路（16）提供刷新定时信号以控制存储器阵列（12）的刷新率。提供可编程熔丝电路（26）以使用计数器（22）对刷新率进行编程。可编程熔丝电路（26）可以在晶圆探针测试或板级老化期间进行编程。可以包括内置的自检（BIST）电路（24）以便于测试。

5. 发明申请

US20050276141A1 Memory with serial input/output terminals for address and data and method therefor 有权
标题翻译：具有用于地址和数据的串行输入/输出端子的存储器及其方法
公开(公告)号：US20050276141A1
公开(公告)日：2005-12-15
申请号：US10854554
申请日：2004-05-26
申请人： Perry Pelley , Carlos Greaves
发明人： Perry Pelley , Carlos Greaves
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/40618 , G11C11/406 , G11C11/40615
摘要： A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.
摘要翻译：存储器（10）具有多个存储单元，用于接收低电压高频差分地址信号的串行地址端口（47）和用于接收高频低电压的串行输入/输出数据端口（52,54）差分数据信号。存储器（10）可以以两种不同模式之一工作，即正常模式和高速缓存行模式。在高速缓存行模式下，内存可以从单个地址访问整个高速缓存行。完全隐藏的刷新模式允许在高速缓存线模式下运行时进行及时的刷新操作。数据通过在多个子阵列（15,17）中交错存储在存储器阵列（14）中。在隐藏的刷新操作模式期间，一个子阵列（15）被访问，而另一个子阵列（17）被刷新。两个或多个存储器（10）可以链接在一起以提供高速低功率存储器系统。

6. 发明授权

US5040144A Integrated circuit with improved power supply distribution 失效
标题翻译：具有改善电源分配的集成电路
公开(公告)号：US5040144A
公开(公告)日：1991-08-13
申请号：US442268
申请日：1989-11-28
申请人： Perry Pelley , Tim P. Egging
发明人： Perry Pelley , Tim P. Egging
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： An integrated circuit with reduced size through improved power supply distribution. A bonding pad supplies V.sub.SS to an integrated circuit memory, which is distributed through a plurality of power supply lines in a first metal layer and a plurality of grid lines in a second metal layer intersecting at right angles. The plurality of grid lines are placed in unused spaced in the second metal layer and are coupled to the power supply lines in the first metal layer. Together the grid lines and the power supply lines provide an improved power supply by lowering the impedance from a point on the integrated circuit to V.sub.SS supplied on the bonding pad. While this technique is ideally suited to memory devices because of the repetitive nature of blocks of memory cells, other types of integrated circuits can also utilize such a power supply distribution technique.
摘要翻译：通过改善电源分配，减小尺寸的集成电路。接合焊盘将VSS提供给集成电路存储器，该集成电路存储器通过第一金属层中的多个电源线和与直角相交的第二金属层中的多个栅格线分布。多个栅格线被放置在未被间隔开的第二金属层中并耦合到第一金属层中的电源线。栅格线和电源线一起通过降低从集成电路上的点到提供在焊盘上的VSS的阻抗来提供改进的电源。虽然这种技术由于存储器单元块的重复性质而非常适用于存储器件，但是其他类型的集成电路也可以利用这种电源分配技术。

7. 发明申请

US20070263474A1 Memory with level shifting word line driver and method thereof 有权
标题翻译：具有电平转换字线驱动器的存储器及其方法
公开(公告)号：US20070263474A1
公开(公告)日：2007-11-15
申请号：US11433998
申请日：2006-05-15
申请人： Thomas Liston , Shahnaz Chowdhury-Nagle , Perry Pelley
发明人： Thomas Liston , Shahnaz Chowdhury-Nagle , Perry Pelley
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C5/144 , G11C8/10
摘要： A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.
摘要翻译：存储器包括包括多个字线的位单元阵列和具有提供预解码值的输出的地址解码电路。地址解码电路包括具有第一栅极氧化物厚度的第一多个晶体管。存储器还包括字线驱动器电路，其具有耦合到地址解码电路的输出的输入和多个输出，每个输出耦合到多个字线中的相应字线。字线驱动器包括具有大于第一栅极氧化物厚度的第二栅极氧化物厚度的第二多个晶体管。还提供了一种操作存储器的方法。

8. 发明申请

US20060250838A1 Method and apparatus for low voltage write in a static random access memory 有权
标题翻译：用于在静态随机存取存储器中低电压写入的方法和装置
公开(公告)号：US20060250838A1
公开(公告)日：2006-11-09
申请号：US11123484
申请日：2005-05-06
申请人： Ravindraraj Ramaraju , Prashant Kenkare , Perry Pelley
发明人： Ravindraraj Ramaraju , Prashant Kenkare , Perry Pelley
IPC分类号： G11C11/00
CPC分类号： G11C11/419
摘要： An integrated circuit memory includes a plurality of memory cells, where each of the plurality of memory cells comprises a first storage node and a second storage node. Each of the plurality of memory cells comprises a transistor coupled between the first and second storage nodes and responsive to an equalization signal. An equalization control circuit provides the equalization signal to selected memory cells of the plurality of memory cells. The equalization control circuit is for equalizing a voltage between the first and second storage nodes to enable to a write operation of the selected memory cells. During the write operation a data signal is provided to a first bit line that swings between a logic high voltage equal to a power supply voltage and a logic low voltage equal to ground potential. The transistor and the equalization control circuit enables reliable memory operation at low power supply voltages.
摘要翻译：集成电路存储器包括多个存储器单元，其中多个存储器单元中的每一个包括第一存储节点和第二存储节点。多个存储单元中的每一个包括耦合在第一和第二存储节点之间并响应均衡信号的晶体管。均衡控制电路将均衡信号提供给多个存储单元的选定存储单元。均衡控制电路用于对第一和第二存储节点之间的电压进行均衡以使得能够对所选存储单元进行写入操作。在写入操作期间，将数据信号提供给在等于电源电压的逻辑高电压和等于地电位的逻辑低电压之间摆动的第一位线。晶体管和均衡控制电路可在低电源电压下实现可靠的存储器操作。

9. 发明申请

US20060170450A1 Integrated circuit with programmable-impedance output buffer and method therefor 有权
标题翻译：具有可编程阻抗输出缓冲器的集成电路及其方法
公开(公告)号：US20060170450A1
公开(公告)日：2006-08-03
申请号：US11047161
申请日：2005-01-31
申请人： Perry Pelley
发明人： Perry Pelley
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： An impedance matching between two integrated circuits is achieved using an impedance measuring circuit in the integrated circuit that contains an impedance-programmable output buffer (IPOB) that is to have its output impedance changed. The impedance measuring device is directly connected to the output of the IPOB so that it is detecting the same impedance that the IPOB will drive and thereby avoids the errors of measuring the resistance of a device that imperfectly models the actual impedance. The impedance measuring device is preferably an analog to digital (A/D) converter that provides a digital output relative to the voltage present on the same terminal as the output of the IPOB. By having the A/D converter on the same integrated circuit as the IPOB, communications difficulties between the A/D converter and the IPOB are minimal.
摘要翻译：使用集成电路中的阻抗测量电路来实现两个集成电路之间的阻抗匹配，该阻抗测量电路包含阻抗可编程输出缓冲器（IPOB），以使其输出阻抗发生变化。阻抗测量装置直接连接到IPOB的输出端，以便它检测到IPOB将驱动的阻抗相同，从而避免测量不实际模拟实际阻抗的器件的电阻误差。阻抗测量装置优选地是模数（A / D）转换器，其提供相对于与IPOB的输出相同的终端上存在的电压的数字输出。通过使A / D转换器与IPOB相同的集成电路，A / D转换器和IPOB之间的通信困难很小。

10. 发明申请

US20050276142A1 Automatic hidden refresh in a dram and method therefor 有权
标题翻译：自动隐藏刷新在一个戏剧和方法
公开(公告)号：US20050276142A1
公开(公告)日：2005-12-15
申请号：US10854298
申请日：2004-05-26
申请人： Perry Pelley
发明人： Perry Pelley
IPC分类号： G11C7/00 , G11C7/10 , G11C11/406
CPC分类号： G11C11/40607 , G11C7/1075 , G11C11/406 , G11C11/40618
摘要： A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.
摘要翻译：存储器（10）具有多个存储单元，用于接收低电压高频差分地址信号的串行地址端口（47）和用于接收高频低电压的串行输入/输出数据端口（52,54）差分数据信号。存储器（10）可以以两种不同模式之一工作，即正常模式和高速缓存行模式。在高速缓存行模式下，内存可以从单个地址访问整个高速缓存行。完全隐藏的刷新模式允许在高速缓存线模式下运行时进行及时的刷新操作。数据通过在多个子阵列（15,17）中交错存储在存储器阵列（14）中。在隐藏的刷新操作模式期间，一个子阵列（15）被访问，而另一个子阵列（17）被刷新。两个或多个存储器（10）可以链接在一起以提供高速低功率存储器系统。

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