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1. 发明授权

US08082137B2 Method and apparatus for thermal modeling and analysis of semiconductor chip designs 有权
标题翻译：用于半导体芯片设计的热建模和分析的方法和装置
公开(公告)号：US08082137B2
公开(公告)日：2011-12-20
申请号：US12137344
申请日：2008-06-11
申请人： Peng Li , Larry Pileggi , Mehdi Asheghi , Rajit Chandra
发明人： Peng Li , Larry Pileggi , Mehdi Asheghi , Rajit Chandra
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5009 , G06F17/5018 , G06F17/5036 , G06F17/5081 , G06F2217/78 , G06F2217/80 , G06F2217/84
摘要： A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.
摘要翻译：提供了半导体芯片设计的建模和热分析的方法和装置。用于执行半导体芯片设计的热测试的新颖方法的一个实施例包括计算半导体芯片设计上的全芯片温度（例如，识别陡峭的热梯度），并根据几何多格网建模全芯片温度技术。几何多格网技术被定制以至少部分地基于设计的物理属性或几何形状来确定半导体芯片设计内的温度。

2. 发明申请

US20080243461A1 METHOD AND APPARATUS FOR THERMAL MODELING AND ANALYSIS OF SEMICONDUCTOR CHIP DESIGNS 有权
标题翻译：用于热模拟和半导体芯片设计分析的方法和装置
公开(公告)号：US20080243461A1
公开(公告)日：2008-10-02
申请号：US12137344
申请日：2008-06-11
申请人： Peng Li , Larry Pileggi , Mehdi Asheghi , Rajit Chandra
发明人： Peng Li , Larry Pileggi , Mehdi Asheghi , Rajit Chandra
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5018 , G06F17/5036 , G06F17/5081 , G06F2217/78 , G06F2217/80 , G06F2217/84
摘要： A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.
摘要翻译：提供了半导体芯片设计的建模和热分析的方法和装置。用于执行半导体芯片设计的热测试的新颖方法的一个实施例包括计算半导体芯片设计上的全芯片温度（例如，识别陡峭的热梯度），并根据几何多格网建模全芯片温度技术。几何多格网技术被定制以至少部分地基于设计的物理属性或几何形状来确定半导体芯片设计内的温度。

3. 发明授权

US07401304B2 Method and apparatus for thermal modeling and analysis of semiconductor chip designs 有权
标题翻译：用于半导体芯片设计的热建模和分析的方法和装置
公开(公告)号：US07401304B2
公开(公告)日：2008-07-15
申请号：US11180353
申请日：2005-07-13
申请人： Peng Li , Larry Pileggi , Mehdi Asheghi , Rajit Chandra
发明人： Peng Li , Larry Pileggi , Mehdi Asheghi , Rajit Chandra
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5018 , G06F17/5036 , G06F17/5081 , G06F2217/78 , G06F2217/80 , G06F2217/84
摘要： A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.
摘要翻译：提供了半导体芯片设计的建模和热分析的方法和装置。用于执行半导体芯片设计的热测试的新颖方法的一个实施例包括计算半导体芯片设计上的全芯片温度（例如，识别陡峭的热梯度），并根据几何多格网建模全芯片温度技术。几何多格网技术被定制以至少部分地基于设计的物理属性或几何形状来确定半导体芯片设计内的温度。

4. 发明申请

US20060031794A1 Method and apparatus for thermal modeling and analysis of semiconductor chip designs 有权
标题翻译：用于半导体芯片设计的热建模和分析的方法和装置
公开(公告)号：US20060031794A1
公开(公告)日：2006-02-09
申请号：US11180353
申请日：2005-07-13
申请人： Peng Li , Larry Pileggi , Mehdi Asheghi , Rajit Chandra
发明人： Peng Li , Larry Pileggi , Mehdi Asheghi , Rajit Chandra
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5018 , G06F17/5036 , G06F17/5081 , G06F2217/78 , G06F2217/80 , G06F2217/84
摘要： A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.
摘要翻译：提供了半导体芯片设计的建模和热分析的方法和装置。用于执行半导体芯片设计的热测试的新颖方法的一个实施例包括计算半导体芯片设计上的全芯片温度（例如，识别陡峭的热梯度），并根据几何多格网建模全芯片温度技术。几何多格网技术被定制以至少部分地基于设计的物理属性或几何形状来确定半导体芯片设计内的温度。

5. 发明申请

US20090224356A1 Method and apparatus for thermally aware design improvement 审中-公开
标题翻译：用于热感知设计改进的方法和装置
公开(公告)号：US20090224356A1
公开(公告)日：2009-09-10
申请号：US11317664
申请日：2005-12-23
申请人： Rajit Chandra
发明人： Rajit Chandra
IPC分类号： H01L25/00 , G06F17/50 , G06F19/00
CPC分类号： G06F17/5009 , G06F17/5018 , G06F17/5036 , G06F17/5045 , G06F17/5081 , G06F2217/78 , G06F2217/80
摘要： Thermally aware design improvement enables increasing performance, reliability, and other related metrics by performing a multi-dimensional thermal analysis of a design of an electronic component in an assumed operating environment. Results of the analysis are then used to drive optimizations and repairs to the design. The performance metrics include maximum and minimum operating frequency, leakage current, power consumption, temperature gradient, absolute temperature, and other related parameters. The reliability metrics include Mean Time Between Failure (MTBF), required burn-in time, and other related parameters. In a related aspect, thermally aware design improvement enables performance driven electronic component design optimization and repair, including improving aspects of the physical design of an included semiconductor die. Improvements include modifying design details such as placement and routing of individual elements of the die. The thermal analysis and subsequent optimization and repair account for and attempt to mitigate the effects of temperature gradient induced problems.
摘要翻译：通过在假设的操作环境中对电子元件的设计进行多维热分析，可以提高感知设计的改进，从而提高性能，可靠性和其他相关指标。然后分析结果用于驱动设计的优化和修复。性能指标包括最大和最小工作频率，漏电流，功耗，温度梯度，绝对温度和其他相关参数。可靠性指标包括平均故障间隔时间（MTBF），所需的老化时间和其他相关参数。在相关方面，热感知设计改进使得能够实现性能驱动的电子部件设计优化和修复，包括改进所包含的半导体管芯的物理设计的方面。改进包括修改设计细节，例如模具的各个元件的放置和布线。热分析和随后的优化和修复考虑并试图减轻温度梯度引起的问题的影响。

6. 发明申请

US20090077508A1 ACCELERATED LIFE TESTING OF SEMICONDUCTOR CHIPS 审中-公开
标题翻译：加速寿命测试的半导体灯
公开(公告)号：US20090077508A1
公开(公告)日：2009-03-19
申请号：US12193752
申请日：2008-08-19
申请人： Daniel I. Rubin , Rajit Chandra , Earl T. Cohen
发明人： Daniel I. Rubin , Rajit Chandra , Earl T. Cohen
IPC分类号： G06F17/50
CPC分类号： G01R31/318364 , G01R31/318357 , G06F17/5018 , G06F17/5036 , G06F2217/10 , G06F2217/76 , G06F2217/78 , G06F2217/80
摘要： Improved techniques for accelerated life testing of a sample of semiconductor chips advantageously enable more effective testing and better estimation of lifetime. Full-chip temperature maps are computed at sets of operating and testing conditions. Evaluating the temperature maps enables operations such as: temperature-aware design changes, including adding and/or configuring heating elements, cooling elements, thermal diodes, or sensors; determination of accelerated testing conditions; avoidance of harmful conditions during accelerated testing; and the better estimation of lifetime. Iteration of the computing and the evaluating refines the accelerated testing conditions. Measuring actual testing conditions and computing a full-chip temperature map using the actual testing conditions enables the estimation of lifetime to account for the actual testing conditions. A lifetime acceleration factor map based, at least in part, on the temperature maps is used to produce the estimated lifetime. Failure analysis improves accuracy of the estimated lifetime.
摘要翻译：用于半导体芯片样本的加速寿命测试的改进的技术有利地实现了更有效的测试和更好地估计寿命。全片温度图是在操作和测试条件的集合下计算的。评估温度图可实现以下操作：温度感知设计更改，包括添加和/或配置加热元件，冷却元件，热二极管或传感器; 确定加速测试条件; 加速测试时避免有害条件; 和更好的寿命估计。迭代计算和评估改进了加速测试条件。使用实际测试条件测量实际测试条件和计算全芯片温度图，可以估计寿命以考虑实际测试条件。至少部分地基于温度图的寿命加速因子图用于产生估计的寿命。故障分析提高了估计寿命的准确性。

7. 发明申请

US20090044156A1 METHOD AND APPARATUS FOR NORMALIZING THERMAL GRADIENTS OVER SEMICONDUCTOR CHIP DESIGNS 审中-公开
标题翻译：用于对半导体芯片设计中的热梯度进行正常化的方法和装置
公开(公告)号：US20090044156A1
公开(公告)日：2009-02-12
申请号：US12257977
申请日：2008-10-24
申请人： Rajit Chandra , Daniel I. Rubin
发明人： Rajit Chandra , Daniel I. Rubin
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method and apparatus for normalizing thermal gradients over semiconductor chip designs is provided. One embodiment of a novel method for normalizing an expected thermal gradient includes determining a location of the thermal gradient in the semiconductor chip design and inserting at least one supplemental heat source into the semiconductor chip design such that the thermal gradient is normalized by heat dissipated by the supplemental heat source.
摘要翻译：提供了一种用于使半导体芯片设计上的热梯度归一化的方法和装置。用于归一化预期热梯度的新方法的一个实施例包括确定半导体芯片设计中的热梯度的位置并将至少一个补充热源插入到半导体芯片设计中，使得通过由补充热源。

8. 发明申请

US20090024969A1 SEMICONDUCTOR CHIP DESIGN HAVING THERMAL AWARENESS ACROSS MULTIPLE SUB-SYSTEM DOMAINS 失效
标题翻译：具有跨多个子系统域的热意识的半导体芯片设计
公开(公告)号：US20090024969A1
公开(公告)日：2009-01-22
申请号：US11317668
申请日：2005-12-23
申请人： Rajit Chandra
发明人： Rajit Chandra
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5018 , G06F17/5036 , G06F17/5081 , G06F2217/78 , G06F2217/80
摘要： A thermally aware design automation suite integrates system-level thermal awareness into the design of semiconductor chips. A thermal analysis engine performs fine-grain thermal simulations of the semiconductor chip based on thermal models and boundary conditions for all thermally significant structures in the chip and the adjacent system that impact the temperature of the semiconductor chip. The thermally aware design automation suite uses the simulations of the thermal analysis engine to repair or otherwise modify the thermally significant structures to equalize temperature variations across the chip, impose specified design assertions on selected portions of the chip, and verify overall chip performance and reliability over designated operating ranges and manufacturing variations. The thermally significant structures are introduced or modified via one or more of: change in number, change in location, and change in material properties.
摘要翻译：热感知设计自动化套件将系统级热感知集成到半导体芯片的设计中。热分析引擎根据影响半导体芯片温度的芯片和相邻系统中的所有热显着结构的热模型和边界条件，对半导体芯片进行细粒度热模拟。热感知设计自动化套件使用热分析引擎的模拟来修复或以其他方式修改热显着结构，以均衡芯片上的温度变化，对芯片的选定部分施加指定的设计断言，并验证整体芯片性能和可靠性指定的工作范围和制造变化。热显着结构通过以下中的一个或多个引入或修改：数量的变化，位置的变化和材料性质的变化。

9. 发明授权

US07472363B1 Semiconductor chip design having thermal awareness across multiple sub-system domains 失效
标题翻译：半导体芯片设计具有跨多个子系统域的热意识
公开(公告)号：US07472363B1
公开(公告)日：2008-12-30
申请号：US11317668
申请日：2005-12-23
申请人： Rajit Chandra
发明人： Rajit Chandra
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5018 , G06F17/5036 , G06F17/5081 , G06F2217/78 , G06F2217/80
摘要： A thermally aware design automation suite integrates system-level thermal awareness into the design of semiconductor chips. A thermal analysis engine performs fine-grain thermal simulations of the semiconductor chip based on thermal models and boundary conditions for all thermally significant structures in the chip and the adjacent system that impact the temperature of the semiconductor chip. The thermally aware design automation suite uses the simulations of the thermal analysis engine to repair or otherwise modify the thermally significant structures to equalize temperature variations across the chip, impose specified design assertions on selected portions of the chip, and verify overall chip performance and reliability over designated operating ranges and manufacturing variations. The thermally significant structures are introduced or modified via one or more of: change in number, change in location, and change in material properties.
摘要翻译：热感知设计自动化套件将系统级热感知集成到半导体芯片的设计中。热分析引擎根据影响半导体芯片温度的芯片和相邻系统中的所有热显着结构的热模型和边界条件，对半导体芯片进行细粒度热模拟。热感知设计自动化套件使用热分析引擎的模拟来修复或以其他方式修改热显着结构，以均衡芯片上的温度变化，对芯片的选定部分施加指定的设计断言，并验证整体芯片性能和可靠性指定的工作范围和制造变化。热显着结构通过以下中的一个或多个引入或修改：数量的变化，位置的变化和材料性质的变化。

10. 发明授权

US07458052B1 Method and apparatus for normalizing thermal gradients over semiconductor chip designs 失效
标题翻译：在半导体芯片设计上对热梯度进行归一化的方法和装置
公开(公告)号：US07458052B1
公开(公告)日：2008-11-25
申请号：US11215783
申请日：2005-08-29
申请人： Rajit Chandra , Daniel I. Rubin
发明人： Rajit Chandra , Daniel I. Rubin
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method and apparatus for normalizing thermal gradients over semiconductor chip designs is provided. One embodiment of a novel method for normalizing an expected thermal gradient includes determining a location of the thermal gradient in the semiconductor chip design and inserting at least one supplemental heat source into the semiconductor chip design such that the thermal gradient is normalized by heat dissipated by the supplemental heat source.
摘要翻译：提供了一种用于使半导体芯片设计上的热梯度归一化的方法和装置。用于归一化预期热梯度的新方法的一个实施例包括确定半导体芯片设计中的热梯度的位置并将至少一个补充热源插入到半导体芯片设计中，使得通过由补充热源。

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