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1. 发明申请

US20070246755A1 METHOD FOR FABRICATING RECESSED GATE MOS TRANSISTOR DEVICE 有权
标题翻译：用于制造接收栅极MOS晶体管器件的方法
公开(公告)号：US20070246755A1
公开(公告)日：2007-10-25
申请号：US11696163
申请日：2007-04-03
申请人： Pei-Ing Lee , Chien-Li Cheng , Shian-Jyh Lin
发明人： Pei-Ing Lee , Chien-Li Cheng , Shian-Jyh Lin
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L27/10861 , H01L27/0629 , H01L27/10876
摘要： A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.
摘要翻译：公开了一种使用TTO多隔离件制造自对准栅极沟槽的方法。提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

2. 发明申请

US20070190712A1 Semiconductor device having a trench gate and method of fabricating the same 审中-公开
标题翻译：具有沟槽栅的半导体器件及其制造方法
公开(公告)号：US20070190712A1
公开(公告)日：2007-08-16
申请号：US11521639
申请日：2006-09-14
申请人： Shian-Jyh Lin , Chien-Li Cheng , Chung-Yuan Lee , Jeng-Ping Lin , Pei-Ing Lee
发明人： Shian-Jyh Lin , Chien-Li Cheng , Chung-Yuan Lee , Jeng-Ping Lin , Pei-Ing Lee
IPC分类号： H01L21/8234
CPC分类号： H01L29/42376 , H01L29/66621
摘要： A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a trench having a sidewall and a bottom using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the trench to form a doped region. The semiconductor substrate underlying the trench is etched to form an extended portion. A gate insulating layer is formed on the trench and the extended portion. A trench gate is formed in the trench and the extended portion.
摘要翻译：提供一种制造具有沟槽栅极的半导体器件的方法。首先，提供其上具有沟槽蚀刻掩模的半导体衬底。使用沟槽蚀刻掩模作为屏蔽，蚀刻半导体衬底以形成具有侧壁和底部的沟槽。杂质通过沟槽掺杂到半导体衬底中以形成掺杂区域。蚀刻沟槽下方的半导体衬底以形成延伸部分。在沟槽和延伸部分上形成栅极绝缘层。在沟槽和延伸部分中形成沟槽栅极。

3. 发明授权

US07446355B2 Electrical device and method for fabricating the same 有权
标题翻译：电气装置及其制造方法
公开(公告)号：US07446355B2
公开(公告)日：2008-11-04
申请号：US11556170
申请日：2006-11-03
申请人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
发明人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/66553 , H01L21/26586 , H01L27/10876 , H01L29/66621 , H01L29/66659
摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.
摘要翻译：公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。多个沟槽嵌入在半导体衬底的存储器阵列区域中。每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

4. 发明申请

US20090011569A1 ELECTRICAL DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：电气设备及其制造方法
公开(公告)号：US20090011569A1
公开(公告)日：2009-01-08
申请号：US12211815
申请日：2008-09-17
申请人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
发明人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
IPC分类号： H01L21/76
CPC分类号： H01L29/66553 , H01L21/26586 , H01L27/10876 , H01L29/66621 , H01L29/66659
摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.
摘要翻译：公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。多个沟槽嵌入在半导体衬底的存储器阵列区域中。每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

5. 发明申请

US20070161205A1 ELECTRICAL DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：电气设备及其制造方法
公开(公告)号：US20070161205A1
公开(公告)日：2007-07-12
申请号：US11556170
申请日：2006-11-03
申请人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
发明人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
IPC分类号： H01L21/76
CPC分类号： H01L29/66553 , H01L21/26586 , H01L27/10876 , H01L29/66621 , H01L29/66659
摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.
摘要翻译：公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。多个沟槽嵌入在半导体衬底的存储器阵列区域中。每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

6. 发明授权

US07795090B2 Electrical device and method for fabricating the same 有权
标题翻译：电气装置及其制造方法
公开(公告)号：US07795090B2
公开(公告)日：2010-09-14
申请号：US12211815
申请日：2008-09-17
申请人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
发明人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/66553 , H01L21/26586 , H01L27/10876 , H01L29/66621 , H01L29/66659
摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.
摘要翻译：公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。多个沟槽嵌入在半导体衬底的存储器阵列区域中。每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

7. 发明授权

US07679137B2 Method for fabricating recessed gate MOS transistor device 有权
标题翻译：凹陷栅极MOS晶体管器件的制造方法
公开(公告)号：US07679137B2
公开(公告)日：2010-03-16
申请号：US11696163
申请日：2007-04-03
申请人： Pei-Ing Lee , Chien-Li Cheng , Shian-Jyh Lin
发明人： Pei-Ing Lee , Chien-Li Cheng , Shian-Jyh Lin
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L27/10861 , H01L27/0629 , H01L27/10876
摘要： A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.
摘要翻译：公开了一种使用TTO多隔离件制造自对准栅极沟槽的方法。提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

8. 发明授权

US07932555B2 Transistor structure and method of making the same 有权
标题翻译：晶体管结构及制作方法
公开(公告)号：US07932555B2
公开(公告)日：2011-04-26
申请号：US11949788
申请日：2007-12-04
申请人： Pei-Ing Lee , Shian-Jyh Lin
发明人： Pei-Ing Lee , Shian-Jyh Lin
IPC分类号： H01L29/66
CPC分类号： H01L27/1087 , H01L27/10841
摘要： A transistor structure includes a gate trench. The gate trench includes a bottle-shape bottom. The bottle-shape bottom includes a first conductive material wider than its top. The top includes a second material in a substrate, a gate structure on the gate trench and electrically connected to the first conductive material, a source/drain doping region adjacent to the gate trench and a gate channel between the source/drain doping region.
摘要翻译：晶体管结构包括栅极沟槽。栅极沟槽包括瓶形底部。瓶形底部包括比其顶部更宽的第一导电材料。顶部包括衬底中的第二材料，栅极沟槽上的栅极结构和电连接到第一导电材料，与栅极沟槽相邻的源极/漏极掺杂区域和源极/漏极掺杂区域之间的栅极沟道。

9. 发明授权

US08044449B2 Memory device with a length-controllable channel 有权
标题翻译：具有长度可控通道的存储器
公开(公告)号：US08044449B2
公开(公告)日：2011-10-25
申请号：US12183021
申请日：2008-07-30
申请人： Shian-Jyh Lin , Hung-Chang Liao , Meng-Hung Chen , Chung-Yuan Lee , Pei-Ing Lee
发明人： Shian-Jyh Lin , Hung-Chang Liao , Meng-Hung Chen , Chung-Yuan Lee , Pei-Ing Lee
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain.
摘要翻译：提供存储器件。存储器件包括衬底，具有形成在衬底中的上部和下部的沟槽，形成在沟槽的下部的沟槽电容器，形成在沟槽电容器的侧壁上并且远离衬底的顶表面，形成在衬底中用作源极/漏极的沟槽的上部侧的第一掺杂区域，形成在沟槽中并电连接到第一掺杂区域的导电层，顶部形成在导电层上的电介质层，形成在顶部电介质层上的栅极，形成在栅极两侧和衬底上的外延层，以及形成在外延层的顶部上用作源极/漏极的第二掺杂区域。

10. 发明申请

US20090020798A1 TRANSISTOR STRUCTURE AND METHOD OF MAKING THE SAME 有权
标题翻译：晶体管结构及其制作方法
公开(公告)号：US20090020798A1
公开(公告)日：2009-01-22
申请号：US11949788
申请日：2007-12-04
申请人： Pei-Ing Lee , Shian-Jyh Lin
发明人： Pei-Ing Lee , Shian-Jyh Lin
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/1087 , H01L27/10841
摘要： A transistor structure includes a gate trench. The gate trench includes a bottle-shape bottom. The bottle-shape bottom includes a first conductive material wider than its top. The top includes a second material in a substrate, a gate structure on the gate trench and electrically connected to the first conductive material, a source/drain doping region adjacent to the gate trench and a gate channel between the source/drain doping region.
摘要翻译：晶体管结构包括栅极沟槽。栅极沟槽包括瓶形底部。瓶形底部包括比其顶部更宽的第一导电材料。顶部包括衬底中的第二材料，栅极沟槽上的栅极结构和电连接到第一导电材料，与栅极沟槽相邻的源极/漏极掺杂区域和源极/漏极掺杂区域之间的栅极沟道。

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