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1. 发明申请

US20110147044A1 SYSTEM TO IMPROVE CORELESS PACKAGE CONNECTIONS AND ASSOCIATED METHODS 有权
标题翻译：系统提高无缝封装连接及相关方法
公开(公告)号：US20110147044A1
公开(公告)日：2011-06-23
申请号：US12642806
申请日：2009-12-19
申请人： Paul M. Harvey , Colm B. O'Reilly , Samuel W. Yang , Yaping Zhou
发明人： Paul M. Harvey , Colm B. O'Reilly , Samuel W. Yang , Yaping Zhou
IPC分类号： H01B5/00 , H01R9/00
CPC分类号： H01L23/645 , H01L21/563 , H01L23/295 , H01L23/49816 , H01L23/552 , H01L2224/13022 , H01L2224/73203 , H01L2924/01077 , H01L2924/3011 , H05K1/0233 , H05K2201/10977 , Y10T29/49147
摘要： A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.
摘要翻译：改进核心封装连接的系统可以包括球栅阵列焊盘和球栅阵列。该系统还可以包括导电连接到相应的球栅阵列焊盘的球栅阵列的连接构件。该系统还可以包括邻近至少一些连接构件和相应的球栅阵列垫定位的磁性底部填充，以增加各自的连接构件的电感。

2. 发明授权

US08222739B2 System to improve coreless package connections 有权
标题翻译：系统改进无芯包连接
公开(公告)号：US08222739B2
公开(公告)日：2012-07-17
申请号：US12642806
申请日：2009-12-19
申请人： Paul M. Harvey , Colm B. O'Reilly , Samuel W. Yang , Yaping Zhou
发明人： Paul M. Harvey , Colm B. O'Reilly , Samuel W. Yang , Yaping Zhou
IPC分类号： H01L23/48 , H01L21/00 , B23K31/02
CPC分类号： H01L23/645 , H01L21/563 , H01L23/295 , H01L23/49816 , H01L23/552 , H01L2224/13022 , H01L2224/73203 , H01L2924/01077 , H01L2924/3011 , H05K1/0233 , H05K2201/10977 , Y10T29/49147
摘要： A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.
摘要翻译：改进核心封装连接的系统可以包括球栅阵列焊盘和球栅阵列。该系统还可以包括导电连接到相应的球栅阵列焊盘的球栅阵列的连接构件。该系统还可以包括邻近至少一些连接构件和相应的球栅阵列垫定位的磁性底部填充，以增加各自的连接构件的电感。

3. 发明授权

US08338949B2 System to improve coreless package connections 有权
公开(公告)号：US08338949B2
公开(公告)日：2012-12-25
申请号：US13369273
申请日：2012-02-08
申请人： Paul M. Harvey , Colm B. O'Reilly , Samuel W. Yang , Yaping Zhou
发明人： Paul M. Harvey , Colm B. O'Reilly , Samuel W. Yang , Yaping Zhou
IPC分类号： H01L23/48 , H01L21/00 , B23K31/02
CPC分类号： H01L23/645 , H01L21/563 , H01L23/295 , H01L23/49816 , H01L23/552 , H01L2224/13022 , H01L2224/73203 , H01L2924/01077 , H01L2924/3011 , H05K1/0233 , H05K2201/10977 , Y10T29/49147
摘要： A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.

4. 发明申请

US20120138349A1 SYSTEM TO IMPROVE CORELESS PACKAGE CONNECTIONS AND ASSOCIATED METHODS 有权
标题翻译：系统提高无缝封装连接及相关方法
公开(公告)号：US20120138349A1
公开(公告)日：2012-06-07
申请号：US13369273
申请日：2012-02-08
申请人： Paul M. Harvey , Colm B. O'Reilly , Samuel W. Yang , Yaping Zhou
发明人： Paul M. Harvey , Colm B. O'Reilly , Samuel W. Yang , Yaping Zhou
IPC分类号： H05K1/02
CPC分类号： H01L23/645 , H01L21/563 , H01L23/295 , H01L23/49816 , H01L23/552 , H01L2224/13022 , H01L2224/73203 , H01L2924/01077 , H01L2924/3011 , H05K1/0233 , H05K2201/10977 , Y10T29/49147
摘要： A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.
摘要翻译：改进核心封装连接的系统可以包括球栅阵列焊盘和球栅阵列。该系统还可以包括导电连接到相应的球栅阵列焊盘的球栅阵列的连接构件。该系统还可以包括邻近至少一些连接构件和相应的球栅阵列垫定位的磁性底部填充，以增加各自的连接构件的电感。

5. 发明申请

US20090302874A1 METHOD AND APPARATUS FOR SIGNAL PROBE CONTACT WITH CIRCUIT BOARD VIAS 审中-公开
标题翻译：用于信号探测的方法和装置与电路板VIAS接触
公开(公告)号：US20090302874A1
公开(公告)日：2009-12-10
申请号：US12135119
申请日：2008-06-06
申请人： Paul M. Harvey , Samuel W. Yang , Yaping Zhou
发明人： Paul M. Harvey , Samuel W. Yang , Yaping Zhou
IPC分类号： G01R1/067
CPC分类号： G01R1/06788 , G01R1/06738
摘要： A method and apparatus for probing a circuit board, is provided. One implementation involves a signal probe including a tip having a plurality of strands of flexible conductive material surrounding the tip, the strands extending out from the tip to provide multiple points of contact with the rim of a via or a conductive barrel of the via when the tip is inserted into the via, the probe tip and probe strands being made of same conductive material; such that aligning the signal probe with the via for engaging the probe tip strands with the via, and inserting the tip into the via, causes bending and flexing of the strands for making contact with a conductor on a top rim of the barrel and inside an inner wall of the barrel.
摘要翻译：提供一种用于探测电路板的方法和装置。一个实施方案涉及信号探针，其包括具有围绕尖端的多个柔性导电材料股的尖端，所述股线从尖端延伸出来，以提供与通孔的通孔或导电筒的边缘的多个接触点尖端插入通孔中，探针尖端和探针线由相同的导电材料制成; 使得信号探针与用于将探针尖端股线与通孔接合并将尖端插入通孔的通孔的信号探针引起股线的弯曲和弯曲以与筒的顶部边缘上的导体接触，并且在一个桶的内壁。

6. 发明授权

US08791372B2 Reducing impedance discontinuity in packages 有权
标题翻译：减少封装中的阻抗不连续性
公开(公告)号：US08791372B2
公开(公告)日：2014-07-29
申请号：US13426892
申请日：2012-03-22
申请人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
发明人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
IPC分类号： H05K1/11
CPC分类号： H05K1/115 , H05K1/0233 , H05K1/112 , H05K3/42 , H05K3/4602 , H05K2201/086 , H05K2201/09536 , H05K2201/096
摘要： A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
摘要翻译：具有电镀通孔（PTH）的器件和/或设备，其被涂覆以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。

7. 发明授权

US08440917B2 Method and apparatus to reduce impedance discontinuity in packages 失效
标题翻译：减少封装中阻抗不连续性的方法和装置
公开(公告)号：US08440917B2
公开(公告)日：2013-05-14
申请号：US11942061
申请日：2007-11-19
申请人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
发明人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
IPC分类号： H05K1/11
CPC分类号： H05K1/115 , H05K1/0233 , H05K1/112 , H05K3/42 , H05K3/4602 , H05K2201/086 , H05K2201/09536 , H05K2201/096
摘要： A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
摘要翻译：一种用于涂覆电镀通孔（PTH）的方法，系统和装置，以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。

8. 发明申请

US20130075148A1 Method and Apparatus to Reduce Impedance Discontinuity in Packages 有权
标题翻译：减少封装阻抗不连续性的方法和装置
公开(公告)号：US20130075148A1
公开(公告)日：2013-03-28
申请号：US13426892
申请日：2012-03-22
申请人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
发明人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
IPC分类号： H05K1/11
CPC分类号： H05K1/115 , H05K1/0233 , H05K1/112 , H05K3/42 , H05K3/4602 , H05K2201/086 , H05K2201/09536 , H05K2201/096
摘要： A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
摘要翻译：一种具有电镀通孔（PTH）的器件和/或设备，其被涂覆以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。

9. 发明申请

US20090126983A1 Method and Apparatus to Reduce Impedance Discontinuity in Packages 失效
标题翻译：减少封装阻抗不连续性的方法和装置
公开(公告)号：US20090126983A1
公开(公告)日：2009-05-21
申请号：US11942061
申请日：2007-11-19
申请人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
发明人： Paul M. Harvey , Douglas O. Powell , Wolfgang Sauter , Yaping Zhou
IPC分类号： H05K1/02 , H05K3/10
CPC分类号： H05K1/115 , H05K1/0233 , H05K1/112 , H05K3/42 , H05K3/4602 , H05K2201/086 , H05K2201/09536 , H05K2201/096
摘要： A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
摘要翻译：一种用于涂覆电镀通孔（PTH）的方法，系统和装置，以减少电子封装中的阻抗不连续性。 PTH通孔嵌入印刷电路板的芯中，该印刷电路板包括芯层，多个堆积层，多个微通孔和多个迹线。迹线将每个微通孔电连接到PTH通孔，形成导电路径。 PTH用诸如镍的磁性金属材料涂覆以增加PTH的内部和外部电导，从而在电子封装中提供信号的阻抗不连续性。

10. 发明申请

US20080073796A1 Electrically Optimized and Structurally Protected Via Structure for High Speed Signals 失效
标题翻译：电子优化和结构保护通过结构的高速信号
公开(公告)号：US20080073796A1
公开(公告)日：2008-03-27
申请号：US11535700
申请日：2006-09-27
申请人： Paul M. Harvey , Kazushige Kawasaki , Gen Yamada
发明人： Paul M. Harvey , Kazushige Kawasaki , Gen Yamada
IPC分类号： H01L23/48
CPC分类号： H05K1/116 , H01L23/49827 , H01L23/66 , H01L2223/6616 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0219 , H05K3/4602 , H05K2201/0792 , H05K2201/09536 , H05K2201/096 , H05K2201/09718 , H05K2201/09781 , H05K2201/09809 , H01L2924/00
摘要： An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a result, the via structure is electrically optimized. The via structure further comprises one or more floating support members placed in close proximity to the via within a via clearance area between the via and the reference planes. The floating support members are “floating” in the sense that they are not in electrical contact with either the via or the reference planes. Thus, they are not provided for purposes of signal propagation but only for structural support. The floating support members may be connected to one another by way of one or more microvia structures.
摘要翻译：提供了用于多层互连基板中的高速信号的电学优化和结构保护的微通孔结构。通孔结构消除了与参考平面的接触的重叠，从而减小了通孔电容，从而减小了通孔结构中的通路阻抗失配。结果，通孔结构被电学优化。通孔结构还包括一个或多个浮动支撑构件，该浮动支撑构件在通孔和参考平面之间的通孔间隙区域内靠近通孔放置。浮动支撑构件在它们不与通孔或参考平面电接触的意义上是“浮动的”。因此，它们不是用于信号传播的目的，而是仅用于结构支持。浮动支撑构件可以通过一个或多个微孔结构彼此连接。

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