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1. 发明授权

US08738979B2 Methods and structure for correlation of test signals routed using different signaling pathways 有权
标题翻译：使用不同信号通路路由的测试信号相关性的方法和结构
公开(公告)号：US08738979B2
公开(公告)日：2014-05-27
申请号：US13434962
申请日：2012-03-30
申请人： Paul J. Smith , Jeffrey K. Whitt , Eugene Saghi , Douglas J. Saxon , Joshua P. Sinykin
发明人： Paul J. Smith , Jeffrey K. Whitt , Eugene Saghi , Douglas J. Saxon , Joshua P. Sinykin
IPC分类号： G01R31/28 , G01R31/319 , G01R31/317
CPC分类号： G01R31/31922 , G01R31/31707 , G01R31/31723 , G01R31/31727 , G01R31/31915
摘要： Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.
摘要翻译：将通过测试信号选择层次的不同路径路由的内部操作信号相关联的方法和结构。该结构包括可操作以产生内部操作信号和时钟信号的电路的功能块。集成电路还包括可操作以接收内部操作信号和时钟信号并且选择性地路由内部操作信号和时钟信号的测试信号选择层级。此外，结构包括控制单元，其可操作以从测试信号选择层级接收时钟信号，以确定通过测试信号选择层级的不同信令路径路由的接收时钟信号之间的延迟。控制单元进一步可操作地基于时钟信号之间的延迟并基于与时钟信号相关的内部操作信号对延迟线进行编程。

2. 发明申请

US20130262946A1 METHODS AND STRUCTURE FOR CORRELATION OF TEST SIGNALS ROUTED USING DIFFERENT SIGNALING PATHWAYS 有权
标题翻译：使用不同信号路径路由的测试信号相关的方法和结构
公开(公告)号：US20130262946A1
公开(公告)日：2013-10-03
申请号：US13434962
申请日：2012-03-30
申请人： Paul J. Smith , Jeffrey K. Whitt , Eugene Saghi , Douglas J. Saxon , Joshua P. Sinykin
发明人： Paul J. Smith , Jeffrey K. Whitt , Eugene Saghi , Douglas J. Saxon , Joshua P. Sinykin
IPC分类号： G06F19/00 , G06F11/25 , G01R31/3177
CPC分类号： G01R31/31922 , G01R31/31707 , G01R31/31723 , G01R31/31727 , G01R31/31915
摘要： Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.
摘要翻译：将通过测试信号选择层次的不同路径路由的内部操作信号相关联的方法和结构。该结构包括可操作以产生内部操作信号和时钟信号的电路的功能块。集成电路还包括可操作以接收内部操作信号和时钟信号并且选择性地路由内部操作信号和时钟信号的测试信号选择层级。此外，结构包括控制单元，其可操作以从测试信号选择层级接收时钟信号，以确定通过测试信号选择层级的不同信令路径路由的接收时钟信号之间的延迟。控制单元进一步可操作地基于时钟信号之间的延迟并基于与时钟信号相关的内部操作信号对延迟线进行编程。

3. 发明申请

US20130257512A1 METHODS AND STRUCTURE FOR UTILIZING EXTERNAL INTERFACES USED DURING NORMAL OPERATION OF A CIRCUIT TO OUTPUT TEST SIGNALS 有权
标题翻译：在电路正常运行时使用外部接口的输出测试信号的方法和结构
公开(公告)号：US20130257512A1
公开(公告)日：2013-10-03
申请号：US13434954
申请日：2012-03-30
申请人： Eugene Saghi , Paul J. Smith , Joshua P. Sinykin , Jeffrey K. Whitt
发明人： Eugene Saghi , Paul J. Smith , Joshua P. Sinykin , Jeffrey K. Whitt
IPC分类号： H03K17/00
CPC分类号： G01R31/00 , G01R31/3172
摘要： Methods and structure are provided for routing internal operational signals of a circuit for output via an external interface. The structure includes an integrated circuit. The integrated circuit comprises a block of circuitry components operable to generate internal operational signals for performing designated functions during normal operation of the circuit, a control unit, a test signal routing hierarchy, and an external interface. The test signal routing hierarchy is coupled to receive the internal operational signals and controllably selects the internal operational signals for acquisition and applies them to the control unit. The external interface provides communications between the integrated circuit and an external device during normal operation of the integrated circuit. The control unit receives the selected internal operational signals from the test signal routing hierarchy, and applies the selected internal operational signals to the external interface during normal operation of the integrated circuit.
摘要翻译：提供了用于路由电路的内部操作信号以经由外部接口输出的方法和结构。该结构包括集成电路。集成电路包括一组电路组件，可操作以产生用于在电路的正常操作期间执行指定功能的内部操作信号，控制单元，测试信号路由层次以及外部接口。耦合测试信号路由层级以接收内部操作信号并可控地选择用于采集的内部操作信号并将其应用于控制单元。外部接口在集成电路的正常操作期间提供集成电路与外部设备之间的通信。控制单元从测试信号路由层次接收所选择的内部操作信号，并且在集成电路的正常操作期间将所选择的内部操作信号施加到外部接口。

4. 发明授权

US08745457B2 Methods and structure for utilizing external interfaces used during normal operation of a circuit to output test signals 有权
标题翻译：用于在电路正常运行期间使用的外部接口输出测试信号的方法和结构
公开(公告)号：US08745457B2
公开(公告)日：2014-06-03
申请号：US13434954
申请日：2012-03-30
申请人： Eugene Saghi , Paul J. Smith , Joshua P. Sinykin , Jeffrey K. Whitt
发明人： Eugene Saghi , Paul J. Smith , Joshua P. Sinykin , Jeffrey K. Whitt
IPC分类号： G01R31/28
CPC分类号： G01R31/00 , G01R31/3172
摘要： Methods and structure are provided for routing internal operational signals of a circuit for output via an external interface. The structure includes an integrated circuit. The integrated circuit comprises a block of circuitry components operable to generate internal operational signals for performing designated functions during normal operation of the circuit, a control unit, a test signal routing hierarchy, and an external interface. The test signal routing hierarchy is coupled to receive the internal operational signals and controllably selects the internal operational signals for acquisition and applies them to the control unit. The external interface provides communications between the integrated circuit and an external device during normal operation of the integrated circuit. The control unit receives the selected internal operational signals from the test signal routing hierarchy, and applies the selected internal operational signals to the external interface during normal operation of the integrated circuit.
摘要翻译：提供了用于路由电路的内部操作信号以经由外部接口输出的方法和结构。该结构包括集成电路。集成电路包括一组电路组件，可操作以产生用于在电路的正常操作期间执行指定功能的内部操作信号，控制单元，测试信号路由层次以及外部接口。耦合测试信号路由层级以接收内部操作信号并可控地选择用于采集的内部操作信号并将其应用于控制单元。外部接口在集成电路的正常操作期间提供集成电路与外部设备之间的通信。控制单元从测试信号路由层次接收所选择的内部操作信号，并且在集成电路的正常操作期间将所选择的内部操作信号施加到外部接口。

5. 发明申请

US20130262945A1 METHODS AND STRUCTURE FOR CORRELATING MULTIPLE TEST OUTPUTS OF AN INTEGRATED CIRCUIT ACQUIRED DURING SEPARATE INSTANCES OF AN EVENT 有权
标题翻译：在事件的独立事件中获取的集成电路的多个测试输出的方法和结构
公开(公告)号：US20130262945A1
公开(公告)日：2013-10-03
申请号：US13434940
申请日：2012-03-30
申请人： Eugene Saghi , Jeffrey K. Whitt , Joshua P. Sinykin
发明人： Eugene Saghi , Jeffrey K. Whitt , Joshua P. Sinykin
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31705 , G01R31/31707
摘要： Methods and structure for correlating multiple sets of test output signals in time are provided. The structure includes an integrated circuit comprising a block of circuitry that generates internal operational signals. The circuit also comprises a test multiplexer (MUX) hierarchy that selects subsets of the internal signals and applies the subsets to a testing element. A clock generator generates a clock signal for the selected signals. A test logic timer receives the clock signal and increments a counter value, and applies the counter value to the testing element. An event detector resets the counter value upon detection of an event, such that a first subset of the internal signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event may be correlated in time with a second subset of the internal signals acquired responsive to detection of a second instance of the event.
摘要翻译：提供了对多组测试输出信号进行时间相关的方法和结构。该结构包括集成电路，其包括产生内部操作信号的电路块。电路还包括测试多路复用器（MUX）层级，其选择内部信号的子集并将子集应用于测试元件。时钟发生器产生所选信号的时钟信号。测试逻辑定时器接收时钟信号并增加计数器值，并将计数器值应用于测试元件。事件检测器在检测到事件时重置计数器值，使得响应于对事件的第一实例的检测而获得的从测试MUX层次结构获取的内部信号的第一子集可以与时间上的第二子集相关联响应于事件的第二实例的检测而获取的内部信号。

6. 发明授权

US08775888B2 Methods and structure for correlating multiple test outputs of an integrated circuit acquired during separate instances of an event 有权
标题翻译：在事件的单独实例期间获取的集成电路的多个测试输出相关联的方法和结构
公开(公告)号：US08775888B2
公开(公告)日：2014-07-08
申请号：US13434940
申请日：2012-03-30
申请人： Eugene Saghi , Jeffrey K. Whitt , Joshua P. Sinykin
发明人： Eugene Saghi , Jeffrey K. Whitt , Joshua P. Sinykin
IPC分类号： G06F11/00
CPC分类号： G01R31/31705 , G01R31/31707
摘要： Methods and structure for correlating multiple sets of test output signals in time are provided. The structure includes an integrated circuit comprising a block of circuitry that generates internal operational signals. The circuit also comprises a test multiplexer (MUX) hierarchy that selects subsets of the internal signals and applies the subsets to a testing element. A clock generator generates a clock signal for the selected signals. A test logic timer receives the clock signal and increments a counter value, and applies the counter value to the testing element. An event detector resets the counter value upon detection of an event, such that a first subset of the internal signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event may be correlated in time with a second subset of the internal signals acquired responsive to detection of a second instance of the event.
摘要翻译：提供了对多组测试输出信号进行时间相关的方法和结构。该结构包括集成电路，其包括产生内部操作信号的电路块。电路还包括测试多路复用器（MUX）层级，其选择内部信号的子集并将子集应用于测试元件。时钟发生器产生所选信号的时钟信号。测试逻辑定时器接收时钟信号并增加计数器值，并将计数器值应用于测试元件。事件检测器在检测到事件时重置计数器值，使得响应于对事件的第一实例的检测而获得的从测试MUX层次结构获取的内部信号的第一子集可以与时间上的第二子集相关联响应于事件的第二实例的检测而获取的内部信号。

7. 发明申请

US20120290875A1 METHODS AND STRUCTURE FOR STORING ERRORS FOR ERROR RECOVERY IN A HARDWARE CONTROLLER 有权
标题翻译：存储硬件控制器中错误恢复错误的方法和结构
公开(公告)号：US20120290875A1
公开(公告)日：2012-11-15
申请号：US13103623
申请日：2011-05-09
申请人： Joshua P. Sinykin , Sreedeepti Reddy , Jeffrey K. Whitt
发明人： Joshua P. Sinykin , Sreedeepti Reddy , Jeffrey K. Whitt
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/0745 , G06F11/0781 , G06F11/0787
摘要： Methods and structure for providing methods and structure for recovering errors in a hardware controller after an overwrite event, such as the detection of another error. In this regard, a link layer of the hardware controller is configured with a register that persistently stores errors until a processor can address them. The link layer is adapted to establish a connection between an initiator and a target and detect errors associated with the connection. As each detected error is overwritten by a subsequently detected error, the link layer register persistently stores the detected errors associated with the connection for recovery after the detected error has been overwritten in the link layer at least until the error can be handled.
摘要翻译：提供方法和结构，用于在覆盖事件（例如检测另一个错误）之后恢复硬件控制器中的错误。在这方面，硬件控制器的链路层配置有持久存储错误的寄存器，直到处理器能够对其进行寻址。链路层适于建立发起者和目标之间的连接并检测与连接相关联的错误。由于每个检测到的错误被随后检测到的错误覆盖，链路层寄存器在至少直到可以处理该错误之后，在检测到的错误已被覆盖在链路层中之后，始终存储与用于恢复的连接相关联的检测到的错误。

8. 发明授权

US08589722B2 Methods and structure for storing errors for error recovery in a hardware controller 有权
标题翻译：存储硬件控制器中错误恢复错误的方法和结构
公开(公告)号：US08589722B2
公开(公告)日：2013-11-19
申请号：US13103623
申请日：2011-05-09
申请人： Joshua P. Sinykin , Sreedeepti Reddy , Jeffrey K. Whitt
发明人： Joshua P. Sinykin , Sreedeepti Reddy , Jeffrey K. Whitt
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0745 , G06F11/0781 , G06F11/0787
摘要： Methods and structure for providing methods and structure for recovering errors in a hardware controller after an overwrite event, such as the detection of another error. In this regard, a link layer of the hardware controller is configured with a register that persistently stores errors until a processor can address them. The link layer is adapted to establish a connection between an initiator and a target and detect errors associated with the connection. As each detected error is overwritten by a subsequently detected error, the link layer register persistently stores the detected errors associated with the connection for recovery after the detected error has been overwritten in the link layer at least until the error can be handled.
摘要翻译：提供方法和结构，用于在覆盖事件（例如检测另一个错误）之后恢复硬件控制器中的错误。在这方面，硬件控制器的链路层配置有持久存储错误的寄存器，直到处理器能够对其进行寻址。链路层适于建立发起者和目标之间的连接并检测与连接相关联的错误。由于每个检测到的错误被随后检测到的错误覆盖，链路层寄存器在至少直到可以处理该错误之后，在检测到的错误已被覆盖在链路层中之后，始终存储与用于恢复的连接相关联的检测到的错误。

9. 发明授权

US08521931B2 Serial input output (SIO) port expansion apparatus and method 有权
标题翻译：串行输入输出（SIO）端口扩展装置及方法
公开(公告)号：US08521931B2
公开(公告)日：2013-08-27
申请号：US12981847
申请日：2010-12-30
申请人： Joshua P. Sinykin , William K. Petty
发明人： Joshua P. Sinykin , William K. Petty
IPC分类号： G06F13/00 , G06F13/12
CPC分类号： G06F13/4282
摘要： An expander device and method for transmitting serial input/output (SIO) data between an initiator device and a plurality of target devices. The expander device includes a processor/controller configured to receive a master data stream from an initiator device and to transmit a returning master data stream to the initiator device. The expander device includes a plurality of target master ports coupled to the processor/controller and configured to transmit split data streams to corresponding target devices coupled thereto and to receive returning split data streams from the target devices. The processor/controller splits the master data stream, based on its data, into a plurality of split data streams, and directs the split data streams to the target master ports based on the data in the split data streams. The processor/controller also assembles a plurality of returning split data streams into the returning master data stream and transmits the returning master data stream to the initiator device.
摘要翻译：一种用于在发起者设备和多个目标设备之间传送串行输入/输出（SIO）数据的扩展器设备和方法。扩展器装置包括处理器/控制器，其被配置为从发起者设备接收主数据流并将返回的主数据流发送到发起者设备。扩展器设备包括耦合到处理器/控制器的多个目标主端口，并且被配置为将分离的数据流发送到与其耦合的相应目标设备并且从目标设备接收返回的分离数据流。处理器/控制器基于其数据将主数据流分解成多个分割数据流，并且基于分割数据流中的数据将分割数据流引导到目标主端口。处理器/控制器还将多个返回的分离数据流组装到返回的主数据流中，并将返回的主数据流发送到发起者设备。

10. 发明授权

US07636798B2 Methods and systems for integrating unique information in SAS interface components 有权
标题翻译：在SAS接口组件中集成独特信息的方法和系统
公开(公告)号：US07636798B2
公开(公告)日：2009-12-22
申请号：US12359446
申请日：2009-01-26
申请人： Steven F. Faulhaber , Joshua P. Sinykin , Matthew K. Freel
发明人： Steven F. Faulhaber , Joshua P. Sinykin , Matthew K. Freel
IPC分类号： G06F3/00 , G06F17/50
CPC分类号： G06F11/006
摘要： Methods and systems for customizing information in a memory associated with a SAS host bus adapter (“HBA”). A SAS HBA typically includes a memory component that stores information common to all SAS HBA's manufactured by a particular vendor (e.g., common instructions and data). In addition, each HBA memory component typically includes some information unique to each HBA (e.g., board trace number, SAS address, configuration page, boot record, etc.). Features and aspects hereof permit pre-programmed memory components to be integrated with a SAS HBA to eliminate a step to program an assembled HBA through a specialized, one-time interaction to add required unique information. Thus a manufacturer may simply integrate a pre-programmed memory component to an otherwise completed HBA assembly to complete the product manufacturing without need for a special programming step. Or a design or test engineer may simply replace a memory component to change unique information on the HBA.
摘要翻译：在与SAS主机总线适配器（“HBA”）相关联的存储器中自定义信息的方法和系统。 SAS HBA通常包括存储由特定供应商制造的所有SAS HBA公用的信息的存储器组件（例如，通用指令和数据）。此外，每个HBA存储器组件通常包括每个HBA唯一的一些信息（例如，板跟踪号，SAS地址，配置页，引导记录等）。其特征和方面允许预先编程的存储器组件与SAS HBA集成，以消除通过专门的一次性交互来编程组装的HBA的步骤，以添加所需的唯一信息。因此，制造商可以简单地将预编程的存储器组件集成到另外完成的HBA组件，以完成产品制造而不需要特殊的编程步骤。或者设计或测试工程师可以简单地替换内存组件来更改HBA上的唯一信息。

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