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1. 发明授权

US08138592B2 Planar array contact memory cards 有权
标题翻译：平面阵列触点记忆卡
公开(公告)号：US08138592B2
公开(公告)日：2012-03-20
申请号：US12142997
申请日：2008-06-20
申请人： Paul Coteus , Kevin C. Gower , Shawn Anthony Hall , Gareth Geoffrey Hougham , Dale J. Pearson
发明人： Paul Coteus , Kevin C. Gower , Shawn Anthony Hall , Gareth Geoffrey Hougham , Dale J. Pearson
IPC分类号： H01L23/02 , H01L23/48 , H01L23/10 , H01L23/34
CPC分类号： G11C5/04 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H05K1/181 , H05K2201/10159 , H01L2224/0401
摘要： A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.
摘要翻译：一种平面存储器模块（PAMM）装置，包括大致平面的卡，包括第一侧和第二侧，所述第一侧具有多个耦合，所述第二侧具有多个连接器，多个存储器件耦合到所述卡经由所述多个联接器的第一部分以及经由所述多个联接器的第二部分耦合到所述卡的至少一个毂芯片。多个联接器中的每一个连接到多个连接器中的相关联的一个。

2. 发明授权

US07863091B2 Planar array contact memory cards 有权
标题翻译：平面阵列触点记忆卡
公开(公告)号：US07863091B2
公开(公告)日：2011-01-04
申请号：US12166773
申请日：2008-07-02
申请人： Paul Coteus , Kevin C. Gower , Shawn Anthony Hall , Gareth Geoffrey Hougham , Dale J. Pearson
发明人： Paul Coteus , Kevin C. Gower , Shawn Anthony Hall , Gareth Geoffrey Hougham , Dale J. Pearson
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L21/82
CPC分类号： G11C5/04 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H05K1/181 , H05K2201/10159 , H01L2224/0401
摘要： A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.
摘要翻译：一种平面存储器模块（PAMM）装置，包括大致平面的卡，包括第一侧和第二侧，所述第一侧具有多个耦合，所述第二侧具有多个连接器，多个存储器件耦合到所述卡经由所述多个联接器的第一部分以及经由所述多个联接器的第二部分耦合到所述卡的至少一个毂芯片。多个联接器中的每一个连接到多个连接器中的相关联的一个。

3. 发明授权

US07566959B2 Planar array contact memory cards 失效
标题翻译：平面阵列触点记忆卡
公开(公告)号：US07566959B2
公开(公告)日：2009-07-28
申请号：US11855356
申请日：2007-09-14
申请人： Paul Coteus , Kevin C. Gower , Shawn Anthony Hall , Gareth Geoffrey Hougham , Dale J. Pearson
发明人： Paul Coteus , Kevin C. Gower , Shawn Anthony Hall , Gareth Geoffrey Hougham , Dale J. Pearson
IPC分类号： H01L23/02 , H01L23/48 , H01L23/10 , H01L23/34
CPC分类号： G11C5/04 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H05K1/181 , H05K2201/10159 , H01L2224/0401
摘要： A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.
摘要翻译：一种平面存储器模块（PAMM）装置，包括大致平面的卡，包括第一侧和第二侧，所述第一侧具有多个耦合，所述第二侧具有多个连接器，多个存储器件耦合到所述卡经由所述多个联接器的第一部分以及经由所述多个联接器的第二部分耦合到所述卡的至少一个毂芯片。多个联接器中的每一个连接到多个连接器中的相关联的一个。

4. 发明授权

US07863089B2 Planar array contact memory cards 有权
公开(公告)号：US07863089B2
公开(公告)日：2011-01-04
申请号：US11855325
申请日：2007-09-14
申请人： Paul Coteus , Kevin C. Gower , Shawn Anthony Hall , Gareth Geoffrey Hougham , Dale J. Pearson
发明人： Paul Coteus , Kevin C. Gower , Shawn Anthony Hall , Gareth Geoffrey Hougham , Dale J. Pearson
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L21/82
CPC分类号： G11C5/04 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H05K1/181 , H05K2201/10159 , H01L2224/0401
摘要： A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.

5. 发明授权

US07282790B2 Planar array contact memory cards 有权
标题翻译：平面阵列触点记忆卡
公开(公告)号：US07282790B2
公开(公告)日：2007-10-16
申请号：US11146495
申请日：2005-06-06
申请人： Paul Coteus , Kevin C. Gower , Shawn Anthony Hall , Dale J. Pearson , Gareth Geoffrey Hougham
发明人： Paul Coteus , Kevin C. Gower , Shawn Anthony Hall , Dale J. Pearson , Gareth Geoffrey Hougham
IPC分类号： H01L23/02 , H01L23/48 , H01L23/10 , H01L23/34
CPC分类号： G11C5/04 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H05K1/181 , H05K2201/10159 , H01L2224/0401
摘要： A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors.
摘要翻译：一种平面存储器模块（PAMM）装置，包括大致平面的卡，包括第一侧和第二侧，所述第一侧具有多个耦合，所述第二侧具有多个连接器，多个存储器件耦合到所述卡经由所述多个联接器的第一部分以及经由所述多个联接器的第二部分耦合到所述卡的至少一个毂芯片。多个联接器中的每一个连接到多个连接器中的相关联的一个。

6. 发明授权

US07897878B2 Compliant penetrating packaging interconnect 有权
标题翻译：兼容穿透包装互连
公开(公告)号：US07897878B2
公开(公告)日：2011-03-01
申请号：US11627430
申请日：2007-01-26
申请人： Paul Coteus , Gareth Geoffrey Hougham , Brian R. Sundlof
发明人： Paul Coteus , Gareth Geoffrey Hougham , Brian R. Sundlof
IPC分类号： H01R12/04 , H05K1/11 , H05K3/36
CPC分类号： H05K3/3436 , H01L23/13 , H01L23/49805 , H01L23/49811 , H01L2924/0002 , H05K3/28 , H05K3/325 , H05K3/4007 , H05K3/4015 , H05K2201/0367 , H05K2201/09745 , H05K2201/1059 , H05K2201/10719 , H05K2203/167 , Y02P70/613 , Y10T29/49126 , Y10T29/4913 , H01L2924/00
摘要： A circuit package is provided. The circuit package includes a plurality of electrically conductive pads located on a bottom surface of the circuit package, wherein at least one pad of the plurality of bottom surface pads has a recession for receiving an electrically conductive protrusion located on a substrate to which the circuit package is to be mounted.
摘要翻译：提供电路封装。电路封装包括位于电路封装的底表面上的多个导电焊盘，其中多个底表面焊盘中的至少一个焊盘具有用于接收位于基板上的导电突起的凹陷，电路封装将被安装。

7. 发明申请

US20080180927A1 Compliant Penetrating Packaging Interconnect 有权
标题翻译：符合渗透包装互连
公开(公告)号：US20080180927A1
公开(公告)日：2008-07-31
申请号：US11627430
申请日：2007-01-26
申请人： Paul Coteus , Gareth Geoffrey Hougham , Brian R. Sundlof
发明人： Paul Coteus , Gareth Geoffrey Hougham , Brian R. Sundlof
IPC分类号： H05K7/10 , H05K3/30
CPC分类号： H05K3/3436 , H01L23/13 , H01L23/49805 , H01L23/49811 , H01L2924/0002 , H05K3/28 , H05K3/325 , H05K3/4007 , H05K3/4015 , H05K2201/0367 , H05K2201/09745 , H05K2201/1059 , H05K2201/10719 , H05K2203/167 , Y02P70/613 , Y10T29/49126 , Y10T29/4913 , H01L2924/00
摘要： A circuit package is provided. The circuit package includes a plurality of electrically conductive pads located on a bottom surface of the circuit package, wherein at least one pad of the plurality of bottom surface pads has a recession for receiving an electrically conductive protrusion located on a substrate to which the circuit package is to be mounted.
摘要翻译：提供电路封装。电路封装包括位于电路封装的底表面上的多个导电焊盘，其中多个底表面焊盘中的至少一个焊盘具有用于接收位于基板上的导电突起的凹陷，电路封装将被安装。

8. 发明申请

US20110272788A1 Computer system wafer integrating different dies in stacked master-slave structures 审中-公开
标题翻译：在堆叠的主从结构中集成不同模具的计算机系统晶片
公开(公告)号：US20110272788A1
公开(公告)日：2011-11-10
申请号：US12777177
申请日：2010-05-10
申请人： Kyu-hyoun Kim , Paul Coteus
发明人： Kyu-hyoun Kim , Paul Coteus
IPC分类号： H01L29/06 , H01L21/00
CPC分类号： H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541
摘要： A stacked 3D integrated circuit structure is manufactured with a common image design for dies which allows diced master dies to cut from the common wafer and diced slave dies cut to be cut from a wafer which has the common image design. In an embodiment is stacked to form a wafer-to-wafer 3D stack before dicing. Master and slave elements which are used for only one kind of separated individual integrated circuit dies which are located along die edges and at die centers before dicing separation of individual integrated circuit chips. A master wafer is shifted ½ way across a die to make cutting along a kerf line effective to provide both master and slave dies. Multiple slaves can be stacked and coupled to a master die which acts as a bus master when attached to a bus to which only the master die is directly connected. The use of a common wafer design minimizes cost of manufacture of chips destined to be stacked as 3D integrated circuits.
摘要翻译：制造堆叠的3D集成电路结构，其具有用于管芯的公共图像设计，其允许切割的主管芯从公共晶片切割并切割成具有共同图像设计的晶片切割的切割从属裸片。在一个实施例中，在切割之前堆叠以形成晶片到晶片3D堆叠。主单元和从元件仅用于单个集成电路芯片切割分离之前沿着芯片边缘和模具中心位置的一种分离的单独集成电路管芯。主晶片沿模具移动1/2路，以便沿着切割线进行切割有效地提供主模和从模。多个从器件可以堆叠并耦合到主引脚，当连接到仅母模直接连接的总线时，主器件用作总线主器件。使用普通晶圆设计可最大限度地降低作为3D集成电路堆叠的芯片的制造成本。

9. 发明申请

US20080055851A1 METHOD AND APPARATUS FOR COOLING AN EQUIPMENT ENCLOSURE THROUGH CLOSED-LOOP LIQUID-ASSISTED AIR COOLING IN COMBINATION WITH DIRECT LIQUID COOLING 失效
公开(公告)号：US20080055851A1
公开(公告)日：2008-03-06
申请号：US11862289
申请日：2007-09-27
申请人： Shawn Hall , Shurong Tian , Paul Coteus , John Karidis , Evan Colgan , Robert Guernsey
发明人： Shawn Hall , Shurong Tian , Paul Coteus , John Karidis , Evan Colgan , Robert Guernsey
IPC分类号： H05K7/20
CPC分类号： H05K7/20754 , G06F1/20 , G06F2200/201
摘要： A method and an apparatus for cooling, preferably within an enclosure, a diversity of heat-generating components, with at least some of the components having high-power densities and others having low-power densities. Heat generated by the essentially relatively few high-power-density components, such as microprocessor chips for example, is removed by direct liquid cooling, whereas heat generated by the more numerous low-power or low-watt-density components, such as memory chips for example, is removed by liquid-assisted air cooling in the form of a closed loop comprising a plurality of heating and cooling zones that alternate along the air path.

10. 发明申请

US20080020601A1 LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES 失效
公开(公告)号：US20080020601A1
公开(公告)日：2008-01-24
申请号：US11865458
申请日：2007-10-01
申请人： Gareth Hougham , Brian Beaman , Evan Colgan , Paul Coteus , Stefano Oggioni , Enrique Vargas
发明人： Gareth Hougham , Brian Beaman , Evan Colgan , Paul Coteus , Stefano Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

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