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1. 发明授权

US08370517B2 Conserving energy in a data processing network 失效
公开(公告)号：US08370517B2
公开(公告)日：2013-02-05
申请号：US09965013
申请日：2001-09-27
申请人： Patrick Joseph Bohrer , Bishop Chapman Brock , Elmootazbellah Nabil Elnozahy , Ramakrishnan Rajamony , Freeman Leigh Rawson, III
发明人： Patrick Joseph Bohrer , Bishop Chapman Brock , Elmootazbellah Nabil Elnozahy , Ramakrishnan Rajamony , Freeman Leigh Rawson, III
IPC分类号： G06F15/16
CPC分类号： G06F1/3203 , G06F1/324 , H04L29/06 , H04L67/1002 , H04L67/1008 , H04L67/1014 , H04L67/1029 , H04L67/1031 , H04L69/24 , H04L69/329 , Y02D10/126
摘要： A data processing network and method for conserving energy in which an initial negotiation between a network server and a switch to which the server is connected is performed to establish an initial operating frequency of the server-switch link. An effective data rate of the server is determined based on network traffic at the server. Responsive to determining that the effective data rate is materially different than the current operating frequency, a subsequent negotiation is performed to establish a modified operating frequency where the modified operating frequency is closer to the effective data rate than the initial operating frequency. The determination of the effective date rate and the contingent initiation of a subsequent negotiation may be repeated periodically during the operating of the network. In one embodiment, the initial and subsequent negotiation are compliant with the IEEE 802.3 standard.

2. 发明授权

US08255591B2 Method and system for managing cache injection in a multiprocessor system 有权
标题翻译：在多处理器系统中管理缓存注入的方法和系统
公开(公告)号：US08255591B2
公开(公告)日：2012-08-28
申请号：US10948407
申请日：2004-09-23
申请人： Patrick Joseph Bohrer , Ahmed Gheith , Peter Heiner Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
发明人： Patrick Joseph Bohrer , Ahmed Gheith , Peter Heiner Hochschild , Ramakrishnan Rajamony , Hazim Shafi , Balaram Sinharoy
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data. In NUMA multiprocessor systems, the completing processor/target memory is chosen for accessibility of the target memory to the processor and associated cache.
摘要翻译：用于管理多处理器系统中的高速缓存注入的方法和装置减少与对称多处理器（SMP）或非均匀存储器访问（NUMA）多处理器环境中的直接存储器访问传输相关联的处理时间。该方法和装置可以检测目标处理器用于DMA完成或直接处理DMA完成到特定处理器，从而使高速缓存注入与执行DMA完成例程的处理器处理注入高速缓存的数据的处理器相连的高速缓存。可以通过确定处理器处理在DMA传输完成时发生的中断来识别目标处理器。或者或与目标处理器识别结合，中断处理程序可以将延迟过程调用排队到目标处理器以处理传送的数据。在NUMA多处理器系统中，选择完成的处理器/目标存储器，以便可访问目标存储器到处理器和相关联的高速缓存。

3. 发明申请

US20120198459A1 ASSIST THREAD FOR INJECTING CACHE MEMORY IN A MICROPROCESSOR 有权
标题翻译：在微处理器中注入高速缓存存储器的辅助螺纹
公开(公告)号：US20120198459A1
公开(公告)日：2012-08-02
申请号：US13434423
申请日：2012-03-29
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

4. 发明授权

US08230422B2 Assist thread for injecting cache memory in a microprocessor 有权
标题翻译：协助在微处理器中注入高速缓存的线程
公开(公告)号：US08230422B2
公开(公告)日：2012-07-24
申请号：US11034546
申请日：2005-01-13
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F9/40 , G06F13/28
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

5. 发明授权

US08949837B2 Assist thread for injecting cache memory in a microprocessor 有权
标题翻译：协助在微处理器中注入高速缓存的线程
公开(公告)号：US08949837B2
公开(公告)日：2015-02-03
申请号：US13434423
申请日：2012-03-29
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F12/00 , G06F9/38 , G06F12/08 , G06F9/48
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

6. 发明授权

US06711650B1 Method and apparatus for accelerating input/output processing using cache injections 失效
标题翻译：用于使用高速缓存注入加速输入/输出处理的方法和装置
公开(公告)号：US06711650B1
公开(公告)日：2004-03-23
申请号：US10289817
申请日：2002-11-07
申请人： Patrick Joseph Bohrer , Ramakrishnan Rajamony , Hazim Shafi
发明人： Patrick Joseph Bohrer , Ramakrishnan Rajamony , Hazim Shafi
IPC分类号： G06F1202
CPC分类号： G06F12/0835
摘要： A method for accelerating input/output operations within a data processing system is disclosed. Initially, a determination is initially made in a cache controller as to whether or not a bus operation is a data transfer from a first memory to a second memory without intervening communications through a processor, such as a direct memory access (DMA) transfer. If the bus operation is such data transfer, a determination is made in a cache memory as to whether or not the cache memory includes a copy of data from the data transfer. If the cache memory does not include a copy of data from the data transfer, a cache line is allocated within the cache memory to store a copy of data from the data transfer.
摘要翻译：公开了一种用于加速数据处理系统内的输入/输出操作的方法。最初，在高速缓存控制器中首先确定总线操作是否是从第一存储器到第二存储器的数据传输，而不需要通过诸如直接存储器访问（DMA）传送的处理器进行通信。如果总线操作是这种数据传输，则在高速缓冲存储器中确定高速缓冲存储器是否包括来自数据传输的数据的副本。如果高速缓冲存储器不包括来自数据传输的数据的副本，则在高速缓冲存储器内分配高速缓存线以存储来自数据传输的数据副本。

7. 发明授权

US10469979B2 Managing data access in mobile devices 有权
公开(公告)号：US10469979B2
公开(公告)日：2019-11-05
申请号：US13459779
申请日：2012-04-30
申请人： Patrick Joseph Bohrer , Ahmed Gheith , James Lyle Peterson
发明人： Patrick Joseph Bohrer , Ahmed Gheith , James Lyle Peterson
IPC分类号： G06F15/16 , H04W4/00
摘要： A method for managing data access in a mobile device is provided in the illustrative embodiments. Using a data manager executing in the mobile device, a data item is configured in a data model. A value parameter of the data item is populated with data and a status parameter of the data item is populated with a status indication. A subscription to the data item is received from a mobile application executing in the mobile device. In response to the subscription, the data and the status of the data item are sent to the mobile application.

8. 发明申请

US20130159990A1 UPDATING FIRMWARE USING A MOBILE COMMUNICATION DEVICE 审中-公开
标题翻译：使用移动通信设备更新固件
公开(公告)号：US20130159990A1
公开(公告)日：2013-06-20
申请号：US13328858
申请日：2011-12-16
申请人： Patrick Joseph Bohrer , Ahmed Gheith
发明人： Patrick Joseph Bohrer , Ahmed Gheith
IPC分类号： G06F9/44
CPC分类号： G06F8/654
摘要： A method, system, and computer program product for updating firmware using a mobile communication device are provided in the illustrative embodiments. At the mobile communication device from a data processing system that includes the firmware, a current version information of the firmware is received. At the mobile communication device, an update of the firmware is stored on a data storage associated with the mobile communication device. From the mobile communication device, the data processing system is instructed to reboot using the update stored on the data storage associated with the mobile communication device.
摘要翻译：在说明性实施例中提供了用于使用移动通信设备更新固件的方法，系统和计算机程序产品。在来自包括固件的数据处理系统的移动通信设备处，接收固件的当前版本信息。在移动通信设备中，固件的更新被存储在与移动通信设备相关联的数据存储器上。从移动通信设备，使用存储在与移动通信设备相关联的数据存储器上的更新来指示数据处理系统重新启动。

9. 发明授权

US06966005B2 Energy caching for a computer 有权
标题翻译：电脑缓存能量
公开(公告)号：US06966005B2
公开(公告)日：2005-11-15
申请号：US10027125
申请日：2001-12-26
申请人： Patrick Joseph Bohrer , Charles Robert Lefurgy
发明人： Patrick Joseph Bohrer , Charles Robert Lefurgy
IPC分类号： G06F1/26 , G06F11/00 , G06F11/30 , H02J7/00
CPC分类号： G06F1/263 , Y10T307/615
摘要： The following are provided for example: methods comprising determining a value for an energy condition affecting at least one computer in a cluster; updating said value continuously; comparing said value with a predefined limit regarding said energy condition; and utilizing at least one energy mode such as storing energy, or operating the computer on stored energy. Systems for executing such methods, and instructions on a computer-usable medium for executing such methods, also are provided for example.
摘要翻译：提供以下例子：方法包括确定影响群集中的至少一台计算机的能量条件的值; 连续更新该值; 将所述值与关于所述能量条件的预定限度进行比较; 并利用至少一种能量模式，例如储存能量，或者将计算机运行在储存的能量上。还提供了用于执行这些方法的系统以及用于执行这些方法的计算机可用介质上的指令。

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