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1. 发明授权

US06191980B1 Single-poly non-volatile memory cell having low-capacitance erase gate 有权
标题翻译：具有低电容擦除栅极的单多晶非易失性存储单元
公开(公告)号：US06191980B1
公开(公告)日：2001-02-20
申请号：US09583505
申请日：2000-05-31
申请人： Patrick J. Kelley , Ross A. Kohler , Chung W. Leung , Richard J. McPartland , Ranbir Singh
发明人： Patrick J. Kelley , Ross A. Kohler , Chung W. Leung , Richard J. McPartland , Ranbir Singh
IPC分类号： G11C1604
CPC分类号： G11C16/0408 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A single-poly flash memory cell has a control device, a switch device, and an erase device, all of which share a common polysilicon floating gate which is designed to retain charge in the programmed memory cell. The memory cell is erased by applying an erase voltage to the tub of the erase device to cause tunneling across the oxide layer separating the floating gate from the rest of the erase device structure. Since a typical tub-to-source/drain breakdown voltage (e.g., 15 volts) is greater than a typical erase voltage (e.g., 10 volts), the memory cell can be safely erased without risking the junction breakdowns that are associated with other prior art single-poly memory cell designs for deep sub-micron technologies (e.g., 0.25-micron and lower).
摘要翻译：单聚焦闪存单元具有控制装置，开关装置和擦除装置，所有这些都共享共同的多晶硅浮动栅极，其被设计为在编程的存储器单元中保持电荷。通过向擦除装置的桶施加擦除电压来擦除存储器单元，以使隔离浮动栅极与擦除装置结构的其余部分的氧化物层的隧穿。由于典型的桶到源极/漏极击穿电压（例如15伏特）大于典型的擦除电压（例如，10伏特），所以可以安全地擦除存储器单元，而不会与与其它先前相关联的结点故障用于深亚微米技术（例如，0.25微米及更低）的单一多晶硅记忆体设计。

2. 发明授权

US07002829B2 Apparatus and method for programming a one-time programmable memory device 失效
标题翻译：用于编程一次性可编程存储器件的装置和方法
公开(公告)号：US07002829B2
公开(公告)日：2006-02-21
申请号：US10675571
申请日：2003-09-30
申请人： Ranbir Singh , Richard J. McPartland , Ross A. Kohler
发明人： Ranbir Singh , Richard J. McPartland , Ross A. Kohler
IPC分类号： G11C17/00
CPC分类号： G11C17/18
摘要： A method and apparatus for opening a fuse formed on a semiconductor substrate. The apparatus comprises a thyristor formed from CMOS device regions and having a one or two control terminals for permitting current to flow through the thyristor into the fuse, for opening the fuse.
摘要翻译：一种用于打开形成在半导体衬底上的熔丝的方法和装置。该装置包括由CMOS器件区形成并具有一个或两个控制端子的晶闸管，用于允许电流流过晶闸管进入保险丝，用于打开保险丝。

3. 发明授权

US06552931B2 Low voltage flash EEPROM memory cell with improved data retention 有权
公开(公告)号：US06552931B2
公开(公告)日：2003-04-22
申请号：US09957124
申请日：2001-09-20
申请人： Richard J. McPartland , Ranbir Singh
发明人： Richard J. McPartland , Ranbir Singh
IPC分类号： G11C1604
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C2216/10
摘要： The present invention provides memory circuit including a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.

4. 发明授权

US08516408B2 Optimization of circuits having repeatable circuit instances 失效
标题翻译：具有可重复电路实例的电路优化
公开(公告)号：US08516408B2
公开(公告)日：2013-08-20
申请号：US12471968
申请日：2009-05-26
申请人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Richard Bruce Dell , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： Techniques for forming a first electronic circuit including a plurality of instances of a repeatable circuit element include the steps of: obtaining a total number of instances of the repeatable circuit element in a design of an IC including the first electronic circuit and at least a second electronic circuit; and configuring at least one functional parameter of the first electronic circuit as a function of the total number of instances of the repeatable circuit element in the IC to thereby satisfy a prescribed minimum composite manufacturing yield of the IC and/or at least one specification of the IC under prescribed operating conditions.
摘要翻译：用于形成包括可重复电路元件的多个实例的第一电子电路的技术包括以下步骤：在包括第一电子电路的IC的设计中获得可重复电路元件的实例的总数，以及至少第二电子电路以及将所述第一电子电路的至少一个功能参数配置为所述IC中的所述可重复电路元件的总数的函数，从而满足所述IC的规定的最小复合制造收益率和/或所述IC的至少一个规格 IC在规定的运行条件下。

5. 发明授权

US07930615B2 Memory device with error correction capability and preemptive partial word write operation 有权
标题翻译：具有纠错能力和抢先部分字写操作的存储器件
公开(公告)号：US07930615B2
公开(公告)日：2011-04-19
申请号：US11756011
申请日：2007-05-31
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1044 , G11C2029/0411
摘要： A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform a partial word write operation in which an error correction code encode process for the given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word. If the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word. The error correction code decode process and an associated correct process are thereby removed from a critical timing path of the partial word write operation.
摘要翻译：存储器件包括耦合到存储器阵列的存储器阵列和纠错电路。存储器装置被配置为执行部分字写入操作，其中在完成针对给定检索字的纠错码解码处理之前，针对给定检索到的字的纠错码编码处理是基于错误校正代码解码过程不会在给定的检索词中指示错误。如果完成时的纠错码解码处理指示给定检索字中的错误，则在纠错电路中校正给定检索字中的错误，并使用校正字重新开始纠错码编码处理。因此，从部分字写入操作的临界定时路径移除纠错码解码处理和相关联的正确处理。

6. 发明申请

US20110055660A1 High-Reliability Memory 有权
标题翻译：高可靠性内存
公开(公告)号：US20110055660A1
公开(公告)日：2011-03-03
申请号：US12550978
申请日：2009-08-31
申请人： Dennis E. Dudeck , Ross A. Kohler , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
发明人： Dennis E. Dudeck , Ross A. Kohler , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1048 , G11C29/42 , G11C29/76 , H03M13/09 , H03M13/19
摘要： A memory circuit includes a memory including a plurality of primary memory elements, and an error correction circuit coupled to the memory and operative to detect an error in at least one of the primary memory elements and to provide corrected data corresponding to the primary memory element. The memory circuit further includes at least one spare memory element and a control circuit operative to replace at least one of the primary memory elements with the spare memory element as a function of results generated by the error correction circuit.
摘要翻译：存储器电路包括存储器，其包括多个主存储器元件，以及错误校正电路，其耦合到存储器并且可操作以检测至少一个主存储器元件中的错误，并提供对应于主存储器元件的校正数据。存储器电路还包括至少一个备用存储器元件和控制电路，其可操作以根据由纠错电路产生的结果将备用存储器元件替换为主存储元件中的至少一个。

7. 发明申请

US20100271064A1 Integrated Circuit Self-Monitored Burn-In 失效
标题翻译：集成电路自我监控老化
公开(公告)号：US20100271064A1
公开(公告)日：2010-10-28
申请号：US12431053
申请日：2009-04-28
申请人： Ross A. Kohler , Richard J. McPartland , Larry Christopher Wall , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Larry Christopher Wall , Wayne E. Werner
IPC分类号： G01R31/02
CPC分类号： G01R31/2856 , G01R31/3187 , G01R31/31935 , G11C29/12 , G11C29/4401 , G11C29/50
摘要： An IC adapted for self-monitored burn-in includes a first memory and at least one BIST circuit coupled to the memory and operative to test the IC by executing a burn-in test and to generate test results indicative of at least one parameter of the burn-in test. The test results are at least temporarily stored in the first memory as a function of a first control signal.
摘要翻译：适于自我监测老化的IC包括第一存储器和耦合到存储器的至少一个BIST电路，并且可操作以通过执行老化测试来测试IC，并产生指示至少一个参数的测试结果老化测试测试结果至少临时存储在第一存储器中作为第一控制信号的函数。

8. 发明授权

US06324095B1 Low voltage flash EEPROM memory cell with improved data retention 有权
标题翻译：低电压闪存EEPROM存储单元，具有改进的数据保留
公开(公告)号：US06324095B1
公开(公告)日：2001-11-27
申请号：US09567521
申请日：2000-05-09
申请人： Richard J. McPartland , Ranbir Singh
发明人： Richard J. McPartland , Ranbir Singh
IPC分类号： G11C1604
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C2216/10
摘要： The present invention provides memory circuit including a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.
摘要翻译：本发明提供了包括控制输入，开关和电压传输结构的存储电路，该结构包括将控制输入电耦合到开关的线性电容器。

9. 发明授权

US08566377B2 Secure random number generator 有权
标题翻译：安全随机数发生器
公开(公告)号：US08566377B2
公开(公告)日：2013-10-22
申请号：US12934510
申请日：2008-05-23
申请人： Edward B. Harris , Richard Hogg , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Edward B. Harris , Richard Hogg , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F11/1008 , G11C11/412 , G11C2029/0411
摘要： A random number generator circuit includes a first memory having multiple storage elements. Each of the storage elements has an initial state corresponding thereto when powered up by a voltage supply source applied to the first memory. The first memory is operative to generate a first signal including multiple bits indicative of the respective initial states of the storage elements. The random number generator circuit further includes an error correction circuit coupled to the first memory. The error correction circuit is operative to receive the first signal and to correct at least one bit in the first signal that is not repeatable upon successive applications of power to the first memory to thereby generate a second signal. The second signal is a random number that is repeatable upon successive applications of power to the first memory.
摘要翻译：随机数发生器电路包括具有多个存储元件的第一存储器。当由施加到第一存储器的电压源供电时，每个存储元件具有与之对应的初始状态。第一存储器用于产生包括指示存储元件的相应初始状态的多个位的第一信号。随机数发生器电路还包括耦合到第一存储器的纠错电路。误差校正电路可操作以接收第一信号并且校正第一信号中的至少一个位，其在连续施加电力到第一存储器从而产生第二信号时不重复。第二信号是在连续向第一存储器施加电力时可重复的随机数。

10. 发明授权

US08023348B2 Method and apparatus for testing a memory device 有权
标题翻译：用于测试存储器件的方法和装置
公开(公告)号：US08023348B2
公开(公告)日：2011-09-20
申请号：US12443776
申请日：2007-10-29
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C29/00
CPC分类号： G11C8/08 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2029/1202
摘要： Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The method includes the steps of: applying a first voltage to at least a given one of the row lines corresponding to at least a given one of the memory cells to be tested, the first voltage being selected to stress at least one performance characteristic of the memory device, the first voltage being different than a second voltage applied to the given one of the row lines for accessing at least one of the memory cells during normal operation of the memory device; exercising the memory device in accordance with prescribed testing parameters; and identifying whether the memory device is operable within prescribed margins of the testing parameters.
摘要翻译：提供了用于测试半导体存储器件的技术。存储器件包括多个存储器单元和连接到存储器单元的多个行线和列线，用于选择性地访问一个或多个存储器单元。该方法包括以下步骤：将至少一个对应于待测试的存储器单元中的给定一个行的行中的至少一个施加第一电压，选择第一电压以强调第一电压的至少一个性能特征存储器件，所述第一电压不同于施加到所述给定行之一行的第二电压，用于在所述存储器件的正常操作期间访问所述存储器单元中的至少一个; 根据规定的测试参数锻炼记忆装置; 以及识别存储器件是否在测试参数的规定余量内可操作。

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