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1. 发明申请

US20050025084A1 Communication bus system operable in a sleep mode and a normal mode 有权
标题翻译：通信总线系统在睡眠模式和正常模式下可操作
公开(公告)号：US20050025084A1
公开(公告)日：2005-02-03
申请号：US10499401
申请日：2002-12-10
申请人： Patrick Heuts , Hendrik Boezen , Harm Voss , Stefan Butselaar
发明人： Patrick Heuts , Hendrik Boezen , Harm Voss , Stefan Butselaar
IPC分类号： G06F1/26 , G06F1/32 , G06F3/00 , H04B1/38 , H04L12/28 , H04L29/00 , H04B7/14
CPC分类号： G06F1/3253 , G06F1/3203 , Y02D10/151
摘要： The communication bus system comprises a plurality of node circuits (10a-d) and a relay circuit (12, 14, 16) coupling the node circuits (10a-d). The relay circuit (12, 14, 16) has a transceiver circuit (124, 164) for relaying messages (21) between the node circuits (10a-d) in a normal mode. The transceiver circuit (124, 164) is powered down in a sleep mode. A detector circuit (120, 160) detects an incoming message (41) when the relay circuit (12, 14, 16) is in a sleep mode. A mode control circuit (122, 162) powers up the transceiver (124, 164) in response to detection of an incoming message (21). Steps are taken that ensure, in the normal mode, that messages (21) will not be relayed in unreadable form. The mode control circuit (122, 162) is arranged to cause the transceiver (124, 164) to relay a remainder (25) of the incoming message (21) after power up. In an embodiment the power needed to transmit the remainder (25) of the message (21) is drained from a capacitor (306) in the power supply (30) before the power supply (30) controls the power supply voltage in the normal mode. In another embodiment the detector circuit (120, 160) temporarily controls the direction of operation of the transceivers (124, 164) at the start of the normal mode instead of further detectors (58a-d) that normally control the direction of operation in the normal mode.
摘要翻译：通信总线系统包括多个节点电路（10a-d）和耦合节点电路（10a-d）的继电器电路（12,14,16）。继电器电路（12,14,16）具有用于以正常模式中继节点电路（10a-d）之间的消息（21）的收发器电路（124,164）。在休眠模式下，收发器电路（124,164）被掉电。当继电器电路（12,14,16）处于睡眠模式时，检测器电路（120,160）检测输入消息（41）。模式控制电路（122,162）响应于输入消息（21）的检测，对收发器（124,164）供电。采取步骤，确保在正常模式下，消息（21）将不会以不可读的形式进行中继。模式控制电路（122,162）被布置成使得收发器（124,164）在上电之后中继输入消息（21）的余数（25）。在一个实施例中，在电源（30）以正常模式控制电源电压之前，将消息（21）的剩余部分（25）所需的功率从电源（30）中的电容器（306）中排出。在另一个实施例中，检测器电路（120,160）在正常模式开始时暂时控制收发器（124,164）的操作方向，而不是通常控制在正常模式下的操作方向的另外的检测器（58a-d）正常模式。

2. 发明申请

US20070159154A1 Voltage regulator circuit arrangement 审中-公开
标题翻译：稳压电路布置
公开(公告)号：US20070159154A1
公开(公告)日：2007-07-12
申请号：US10586832
申请日：2005-01-10
申请人： Aloysius Boomkamp , Harm Voss , Stefan Butselaar , Clemens Gerhardus Haas , Gerrit Bollen , Ruurd Visser
发明人： Aloysius Boomkamp , Harm Voss , Stefan Butselaar , Clemens Gerhardus Haas , Gerrit Bollen , Ruurd Visser
IPC分类号： G05F3/16
CPC分类号： G06F1/26
摘要： The invention relates to a voltage regulator circuit arrangement comprising a voltage regulator for generating an out-put voltage in dependence of a reference signal, characterized in that a reference signal generation circuit is provided for generating said reference signal comprising a plurality of inputs connected to internal terminals, whereby a sub-set of said plurality internal terminals is connected to an external terminal.
摘要翻译：本发明涉及一种电压调节器电路装置，其包括用于根据参考信号产生输出电压的电压调节器，其特征在于，提供用于产生所述参考信号的参考信号产生电路，所述参考信号产生电路包括连接到内部的多个输入端子，由此所述多个内部端子的子集连接到外部端子。

3. 发明申请

US20050246555A1 Transition detection at input of integrated circuit device 失效
标题翻译：集成电路设备输入端的过渡检测
公开(公告)号：US20050246555A1
公开(公告)日：2005-11-03
申请号：US10525579
申请日：2003-07-22
申请人： Clemens Gerhardus De Haas , Cecilius Gerardus Kwakernaat , Stefan Butselaar
发明人： Clemens Gerhardus De Haas , Cecilius Gerardus Kwakernaat , Stefan Butselaar
IPC分类号： G06F1/24 , H03K5/04 , H03K5/08 , H03K5/1252 , H03K19/0175 , G06F1/26 , G06F1/28 , G06F1/30
CPC分类号： G06F1/24 , H03K5/04 , H03K5/08 , H03K5/1252
摘要： An integrated circuit has an input connection for connecting an external signal conductor that passes signals to execute functions in the device. The external signal conductor can pick up strong interfering signals with high frequency content, for example when the device is used in a car. To protect against unintended execution of functions the device contains a timer circuit comprising a capacitance and a current supplying circuit coupled to an integration node. A discharge diode is coupled between the input connection and the integration node, with a polarity such that the discharge diode, when in forward bias, is capable of draining current from the current supplying circuit. A detector is coupled to the integration node for generating a signal to be supplied to the integrated circuit device to respond to a signal transition on the conductor. The diode serves to reset integration on the integration node before the detector detects the transition in case of short pulses. By using a diode instead of a switching transistor the circuit is more robust against the effect of interfering pulses.
摘要翻译：集成电路具有用于连接外部信号导体的输入连接，该外部信号导体通过信号以执行装置中的功能。外部信号导体可以拾取高频内容的强干扰信号，例如当该装置用于汽车时。为了防止意外执行功能，该装置包含定时器电路，该定时器电路包括耦合到集成节点的电容和电流供应电路。放电二极管耦合在输入连接和积分节点之间，其极性使得放电二极管在正向偏压时能够从电流供应电路引出电流。检测器耦合到积分节点，用于产生要提供给集成电路器件的信号以响应导体上的信号转变。在检测器检测到短脉冲情况下的转换之前，二极管用于复位积分节点上的积分。通过使用二极管代替开关晶体管，该电路相对于干扰脉冲的影响更为鲁棒。

4. 发明授权

US08692583B2 Differential integrated input circuit 有权
标题翻译：差分集成输入电路
公开(公告)号：US08692583B2
公开(公告)日：2014-04-08
申请号：US13218663
申请日：2011-08-26
申请人： Aloysius Johannes Maria Boomkamp , Stefan Butselaar , Ben Gelissen , Mehdi El Ghorba , Cornelis Klaas Waardenburg
发明人： Aloysius Johannes Maria Boomkamp , Stefan Butselaar , Ben Gelissen , Mehdi El Ghorba , Cornelis Klaas Waardenburg
IPC分类号： H03K5/22
CPC分类号： H03F3/4508 , H03F3/45179 , H03F2203/45306 , H03F2203/45318 , H03F2203/45352 , H03F2203/45374 , H03F2203/45394 , H03F2203/45562 , H03F2203/45594 , H03F2203/45604 , H03F2203/45658 , H03F2203/45702 , H03K5/2418 , H03K5/2481
摘要： An apparatus, system, and method are provided for a differential integrated input circuit. The apparatus includes n-type semiconductor devices and p-type semiconductor devices. The p-type semiconductor devices are cross-coupled with the n-type semiconductor devices. Each of the p-type semiconductor devices biases a corresponding n-type semiconductor device.
摘要翻译：为差分集成输入电路提供了一种装置，系统和方法。该装置包括n型半导体器件和p型半导体器件。 p型半导体器件与n型半导体器件交联。每个p型半导体器件偏置相应的n型半导体器件。

5. 发明申请

US20130049845A1 DIFFERENTIAL INTEGRATED INPUT CIRCUIT 有权
标题翻译：差分集成输入电路
公开(公告)号：US20130049845A1
公开(公告)日：2013-02-28
申请号：US13218663
申请日：2011-08-26
申请人： Aloysius Johannes Maria Boomkamp , Stefan Butselaar , Ben Gelissen , Mehdi El Ghorba , Cornelis Klaas Waardenburg
发明人： Aloysius Johannes Maria Boomkamp , Stefan Butselaar , Ben Gelissen , Mehdi El Ghorba , Cornelis Klaas Waardenburg
IPC分类号： G05F3/02 , H01L27/12
CPC分类号： H03F3/4508 , H03F3/45179 , H03F2203/45306 , H03F2203/45318 , H03F2203/45352 , H03F2203/45374 , H03F2203/45394 , H03F2203/45562 , H03F2203/45594 , H03F2203/45604 , H03F2203/45658 , H03F2203/45702 , H03K5/2418 , H03K5/2481
摘要： An apparatus, system, and method are provided for a differential integrated input circuit. The apparatus includes n-type semiconductor devices and p-type semiconductor devices. The p-type semiconductor devices are cross-coupled with the n-type semiconductor devices. Each of the p-type semiconductor devices biases a corresponding n-type semiconductor device.
摘要翻译：为差分集成输入电路提供了一种装置，系统和方法。该装置包括n型半导体器件和p型半导体器件。 p型半导体器件与n型半导体器件交叉耦合。每个p型半导体器件偏置相应的n型半导体器件。

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