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1. 发明授权

US07191079B2 Oscilloscope having advanced triggering capability 有权
标题翻译：示波器具有先进的触发能力
公开(公告)号：US07191079B2
公开(公告)日：2007-03-13
申请号：US11089883
申请日：2005-03-23
申请人： Patrick A. Smith , Que Thuy Tran , John C. Delacy , Daniel G. Knierim , David L. Kelly , John C. Calvin
发明人： Patrick A. Smith , Que Thuy Tran , John C. Delacy , Daniel G. Knierim , David L. Kelly , John C. Calvin
IPC分类号： G01R13/00
CPC分类号： G01R13/32 , G01R13/0254
摘要： An advanced trigger circuit includes two trigger decoders, each triggering on one of respective pluralities of continuous-time trigger events. In one embodiment, a programmable timer begins timing in response to an output signal of the first trigger decoder and generates an end-of-time signal at the expiration of its time period. A reset circuit resets the first trigger decoder if the second selected continuous-time trigger event failed to occur before the end-of-time signal was generated. In another embodiment, a reset decoder generates a reset signal in response to an occurrence of a selected continuous-time trigger event. The reset circuit is responsive to the reset signal for resetting the first trigger decoder if the second selected continuous-time trigger event failed to occur before the reset signal was generated. In other embodiments, the advanced trigger circuit triggers on a serial lane skew violation or on a beacon width violation.
摘要翻译：高级触发电路包括两个触发解码器，每个触发解码器在相应的多个连续时间触发事件之一上触发。在一个实施例中，可编程定时器响应于第一触发解码器的输出信号开始定时，并且在其时间段期满时产生结束时间信号。如果在生成结束时间信号之前第二次选择的连续时间触发事件不能发生，则复位电路复位第一触发解码器。在另一个实施例中，复位解码器响应于所选择的连续时间触发事件的发生而产生复位信号。如果在产生复位信号之前第二选择的连续时间触发事件不能发生，则复位电路响应于复位信号来复位第一触发解码器。在其他实施例中，高级触发电路在串行通道偏斜违规或信标宽度冲突时触发。

2. 发明授权

US07652598B2 Serial data analysis improvement 失效
标题翻译：串行数据分析改进
公开(公告)号：US07652598B2
公开(公告)日：2010-01-26
申请号：US11925685
申请日：2007-10-26
申请人： Shane A. Hazzard , Que Thuy Tran , Kayla R. Klingman , David L. Kelly , Patrick A. Smith , Daniel G. Knierim
发明人： Shane A. Hazzard , Que Thuy Tran , Kayla R. Klingman , David L. Kelly , Patrick A. Smith , Daniel G. Knierim
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H04J3/076 , H04L25/14 , H04L25/4908
摘要： A method for improving performance and flexibility of serial data analysis in test instruments, is independent of data bit rate, encoding scheme or communication protocol embodied in the serial data. The serial data is input to a transmitter section, where it is demultiplexed into a plurality of multi-bit lanes, such as n bits for each of N lanes. The N lanes are then encoded into characters, the encoded N lanes having m bits per lane where m>n. Bit stuffing is used to adjust the data rate and/or to insert qualifiers. The stuffed, encoded N lanes are then multiplexed into N serial lanes, which are output from the transmitter section for input to a receiver section at a data rate that is optimal for the receiver section. In the receiver section the N lanes are deserialized, decoded and input to a word recognizer to generate a trigger event signal.
摘要翻译：用于提高测试仪器中串行数据分析的性能和灵活性的方法独立于串行数据中体现的数据比特率，编码方案或通信协议。串行数据被输入到发射机部分，其中它被解复用为多个多比特通道，例如N个通道中的每一个的n比特。然后将N个通道编码为字符，编码的N个通道在每个通道中具有m位，其中m> n。位填充用于调整数据速率和/或插入限定符。填充的编码N通道然后被复用到N个串行通道中，N个串行通道从发送器部分输出，以对于接收机部分最佳的数据速率输入到接收机部分。在接收器部分中，N个通道被反序列化，解码并输入到字识别器以产生触发事件信号。

3. 发明授权

US08866468B2 DF/dT trigger system and method 有权
标题翻译： DF / dT触发系统和方法
公开(公告)号：US08866468B2
公开(公告)日：2014-10-21
申请号：US13015128
申请日：2011-01-27
申请人： Patrick A. Smith , Daniel G. Knierim , John C. Calvin , Shane A. Hazzard
发明人： Patrick A. Smith , Daniel G. Knierim , John C. Calvin , Shane A. Hazzard
IPC分类号： G01R23/14 , G01R13/02 , H03L7/093 , G01R23/02 , G01R31/317
CPC分类号： G01R13/0254 , G01R23/02 , G01R31/31727 , H03L7/093
摘要： A dF/dT trigger system and method includes instantaneously triggering on a frequency deviation of a data signal, which can be associated with an SSC signal. After receiving a signal at an input terminal of a test and measurement instrument, the signal is low-pass filtered and transmitted to trigger circuitry. When a frequency deviation rate in the filtered signal exceeds or crosses one or more thresholds, a trigger event is produced. Also disclosed is a test and measurement instrument including an input terminal to receive the signal, input circuitry to receive and process the signal, and dF/dT trigger circuitry configured to receive the signal and produce a trigger event when a frequency deviation in the signal exceeds or crosses one or more thresholds.
摘要翻译： dF / dT触发系统和方法包括立即触发可与SSC信号相关联的数据信号的频率偏差。在测试和测量仪器的输入端接收到信号后，信号被低通滤波并传输到触发电路。当滤波信号中的频率偏差率超过或超过一个或多个阈值时，产生触发事件。还公开了一种测试和测量仪器，包括用于接收信号的输入端子，用于接收和处理信号的输入电路，以及配置为当信号中的频率偏差超过信号时接收信号并产生触发事件的dF / dT触发电路或跨越一个或多个阈值。

4. 发明授权

US07983332B2 Eye violation and excess jitter trigger 有权
标题翻译：眼睛违规和过度抖动触发
公开(公告)号：US07983332B2
公开(公告)日：2011-07-19
申请号：US11938384
申请日：2007-11-12
申请人： Patrick A. Smith , Daniel G. Knierim
发明人： Patrick A. Smith , Daniel G. Knierim
IPC分类号： H04B3/46
CPC分类号： G01R31/3171 , G01R13/0218 , H04L1/205 , H04L1/24
摘要： An eye violation and excess jitter trigger for a digital signal uses a mask within a unit interval of the digital signal, such as a rectangular mask having corners defined by a high threshold, a low threshold, an early clock and a late clock, the early and late clocks being derived from a reference clock. The reference clock may be a recovered clock derived from the digital signal or from high and low threshold comparator outputs, or may be an external clock. For the excess jitter trigger, which is a special case of the eye violation trigger, the high and low thresholds are essentially equal. A status of the digital signal with respect to the mask is determined using the high and low thresholds and the early and late clocks, and a violation signal is output when the status indicates that a portion of the digital signal crossed into the mask. The violation signal may then be used to trigger data acquisition or for other purposes.
摘要翻译：数字信号的眼睛违规和过度抖动触发在数字信号的单位间隔内使用掩模，例如具有由高阈值，低阈值，早期钟和迟钟定义的角的矩形掩模，早期并且延迟的时钟源自参考时钟。参考时钟可以是从数字信号或从高和低阈值比较器输出导出的恢复时钟，或者可以是外部时钟。对于过度抖动触发，这是眼睛违规触发的特殊情况，高低阈值基本相等。使用高低阈值和早期和晚期时钟来确定数字信号相对于掩模的状态，并且当状态指示数字信号的一部分越过掩模时，输出违规信号。然后可以使用违规信号来触发数据采集或用于其他目的。

5. 发明申请

US20140002292A1 ALMOST REAL-TIME SAMPLING FOR GROUND-PENETRATING RADAR IMPULSES 有权
标题翻译： ALMOST实时采样雷达射线雷达
公开(公告)号：US20140002292A1
公开(公告)日：2014-01-02
申请号：US13536813
申请日：2012-06-28
申请人： Daniel G. Knierim
发明人： Daniel G. Knierim
IPC分类号： G01S13/88
CPC分类号： G01S13/885 , G01S7/411 , G01S7/5273 , G01S13/003 , G01S13/0209 , G01S13/222 , G01V3/12
摘要： A ground-penetrating RADAR-based system can include a transmitter configured to transmit multiple RADAR impulses and a receiver configured to receive a signal comprising return waves generated responsive to the transmitted RADAR impulses. The signal can include a direct wave portion and a reflected wave portion. The system can also include a processing unit configured to analyze the return waves by determining the direct wave portion, fitting the direct wave portion to determine parametric information corresponding to the return waves, determining the reflected wave portion, determining characteristics of the reflected wave portion based on the parametric information, and comparing the determined characteristics against known characteristics.
摘要翻译：基于地面穿透的基于RADAR的系统可以包括被配置为发送多个RADAR脉冲的发射机和被配置为接收包括响应于所发射的RADAR脉冲产生的返回波的信号的接收机。信号可以包括直接波段和反射波部分。该系统还可以包括：处理单元，被配置为通过确定直接波段来分析返回波，拟合直接波部分以确定对应于返回波的参数信息，确定反射波部分，基于反射波部分的特性确定对参数信息进行比较，并将确定的特征与已知特征进行比较。

6. 发明授权

US07035325B2 Jitter measurement using mixed down topology 失效
标题翻译：使用混合向下拓扑进行抖动测量
公开(公告)号：US07035325B2
公开(公告)日：2006-04-25
申请号：US09865971
申请日：2001-05-25
申请人： Jeffrey A. Kleck , Dan H. Wolaver , Daniel G. Knierim
发明人： Jeffrey A. Kleck , Dan H. Wolaver , Daniel G. Knierim
IPC分类号： H04B17/00 , H04B3/46 , H04L7/00
CPC分类号： H04L1/205
摘要： A jitter measurement method using a down-mixing or down-converting topology in a jitter measurement system preserves the jitter UI rather than the jitter seconds. An input serial data stream at a high baud is mixed with a stable local oscillator frequency that is close to that of the high baud. The difference between the high baud and the local oscillator frequency is passed by a filter as a lower rate serial stream. A clock recovery circuit recovers a lower rate clock from the lower rate serial stream, or an amplitude modulation removal stage converts the lower rate serial stream to a lower rate NRZ signal, or the lower rate serial signal is digitized. Jitter measurement is performed by a jitter measurement stage on the lower rate clock, the lower rate NRZ signal, or the digitized lower rate serial signal.
摘要翻译：在抖动测量系统中使用下混合或下变频拓扑的抖动测量方法可以保留抖动UI而不是抖动秒。高波特率的输入串行数据流与稳定的本地振荡器频率混合，接近高波特率。高波特率和本地振荡器频率之间的差异由滤波器作为较低速率串行流传递。时钟恢复电路从较低速率串行流中恢复较低速率的时钟，或者幅度调制去除阶段将较低速率串行流转换为较低速率的NRZ信号，或者较低速率串行信号被数字化。抖动测量通过低速时钟，较低速率NRZ信号或数字化低速率串行信号的抖动测量级进行。

7. 发明授权

US06720828B2 Apparatus and method for compensating a high impedance attenuator 有权
标题翻译：用于补偿高阻抗衰减器的装置和方法
公开(公告)号：US06720828B2
公开(公告)日：2004-04-13
申请号：US09992058
申请日：2001-11-21
申请人： Theodore G. Nelson , Michael P. Khaw , Daniel G. Knierim , John F. Stoops
发明人： Theodore G. Nelson , Michael P. Khaw , Daniel G. Knierim , John F. Stoops
IPC分类号： H03G320
CPC分类号： H03H11/24
摘要： A high impedance attenuator for use in a test and measurement instrument employs compensation to adjust the low frequency attenuation to match the high frequency attenuation exhibited by the attenuator, rather than attempting to adjust the high frequency attenuation exhibited by the attenuator. In an alternate embodiment of the invention, compensation to adjust low frequency attenuation is employed in a feedback loop and an opposite compensation is applied in a parallel attenuation stage to stabilize the input resistance. In yet another embodiment of the invention, compensation to adjust low frequency attenuation is employed by means of an R-C time constant of an additional R-C circuit in a feed forward loop. This additional time constant is matched to the R-C time constant of the input R-C network. The input resistance of the attenuator is not changed.
摘要翻译：用于测试和测量仪器的高阻抗衰减器采用补偿来调节低频衰减，使其与衰减器所显示的高频衰减相匹配，而不是试图调整衰减器所表现的高频衰减。在本发明的替代实施例中，在反馈环路中采用用于调节低频衰减的补偿，并且在并联衰减级中施加相反的补偿以稳定输入电阻。在本发明的另一个实施例中，通过前馈环路中附加的R-C电路的R-C时间常数来采用用于调整低频衰减的补偿。这个额外的时间常数与输入R-C网络的R-C时间常数相匹配。衰减器的输入电阻不变。

8. 发明授权

US5530454A Digital oscilloscope architecture for signal monitoring with enhanced duty cycle 失效
标题翻译：数字示波器架构，用于增强占空比的信号监控
公开(公告)号：US5530454A
公开(公告)日：1996-06-25
申请号：US227213
申请日：1994-04-13
申请人： Eric P. Etheridge , Gordon W. Shank , Daniel G. Knierim
发明人： Eric P. Etheridge , Gordon W. Shank , Daniel G. Knierim
IPC分类号： G01R13/20 , G01R13/02 , G01R13/26 , G01R13/34 , G09G5/36
CPC分类号： G01R13/345 , G01R13/0227 , G01R13/26
摘要： To increase the percentage of time that an input signal is actively monitored, a digital oscilloscope has an acquisition system (100) that includes an analog-to-digital converter (15), an acquisition memory (40), an acquisition rasterizer (50), and a raster acquisition memory (60). The rasterizer contains circuitry (52) for concurrently rasterizing and combining the results of several acquisitions together and with a stored composite raster image to produce a new composite raster image, while additional acquisition records are being created and stored in the acquisition memory. A display system (200) takes the composite raster images after they contain the results of many acquisitions and overlays these single-bit raster images on a multi-bit raster image that is then decremented to produce a simulated persistence effect. The number of new pixels turned on as a result of each acquisition can be counted during the combining process and used to stop acquisitions, signal the operator, or specially treat that particular acquisition when the number of new pixels created by a particular acquisition exceeds a predetermined value. Acquisition circuitry for multiple channels can be used on one channel to further increase the percentage of time that the signal is monitored.
摘要翻译：为了增加主动监测输入信号的时间百分比，数字示波器具有采集系统（100），其包括模数转换器（15），采集存储器（40），采集光栅化器（50），以及光栅采集存储器（60）。光栅化器包括电路（52），用于同时光栅化并将多个采集的结果组合在一起并与存储的复合光栅图像组合以产生新的复合光栅图像，同时另外获取记录被创建并存储在采集存储器中。显示系统（200）在它们包含多次获取的结果并且将这些单位光栅图像叠加在多位光栅图像上之后，采用复合光栅图像，然后将其减少以产生模拟的持续效应。作为每次获取的结果而打开的新像素的数量可以在组合处理期间被计数，并且用于停止采集，向操作者发信号，或者当由特定采集创建的新像素的数量超过预定值时特别处理该特定采集值。可以在一个通道上使用多个通道的采集电路，以进一步增加监控信号的时间百分比。

9. 发明授权

US5399988A F.sub.T doubler amplifier 失效
标题翻译： FT倍频放大器
公开(公告)号：US5399988A
公开(公告)日：1995-03-21
申请号：US182606
申请日：1994-01-14
申请人： Daniel G. Knierim
发明人： Daniel G. Knierim
IPC分类号： H03F1/30 , H03F1/32 , H03F1/42 , H03F3/34 , H03F3/45
CPC分类号： H03F3/45197 , H03F1/3211 , H03F3/45071
摘要： A transistor amplifier having a main amplifier exhibiting a substantially doubled f.sub.T characteristic and having error cancellation circuitry, wherein the standing current of the error cancellation circuitry is reused in powering the main amplifier. The main amplifier comprises an outer differential pair of transistors and an inner differential pair of transistors, each differential pair having an inverting side and a non-inverting side. The collectors of the transistors of the non-inverting side of the differential pairs are connected, respectively, at a first current summing node. The collectors of the transistors of the inverting side of the differential pairs are connected, respectively, at a second current summing node. The f.sub.T doubler transistor amplifier also employs level shifter stages to shift the input signals for application to the error cancellation circuitry, the level shift being an amount predetermined to substantially center the error cancellation circuitry in its dynamic range of operation. The f.sub.T doubler transistor amplifier also provides current sources which contribute to powering the main amplifier and which source current in amounts predetermined to control positive feedback from the main amplifier to the error cancellation circuitry so as to enhance accurate cancellation of errors.
摘要翻译：具有主放大器的晶体管放大器具有大致双倍的fT特性并且具有误差消除电路，其中误差消除电路的驻电电流被重新用于为主放大器供电。主放大器包括外部差分对晶体管和内部差分对晶体管，每个差分对具有反相侧和非反相侧。差分对的非反相侧的晶体管的集电极分别连接在第一电流求和节点处。差分对的反相侧的晶体管的集电极分别在第二电流求和节点处连接。 fT倍增晶体管放大器还采用电平移位器级将输入信号移位到误差消除电路，电平移位是预定的量，以使误差消除电路在其动态操作范围内基本居中。 fT倍增晶体管放大器还提供电流源，其有助于为主放大器供电，并且预定的源电流用于控制从主放大器到误差消除电路的正反馈，以便增强误差的精确消除。

10. 发明申请

US20130022133A1 Wideband Balun Structure 有权
标题翻译：宽带平衡臂结构
公开(公告)号：US20130022133A1
公开(公告)日：2013-01-24
申请号：US13341916
申请日：2011-12-31
申请人： Daniel G. Knierim , James S. Lamb , Josiah A. Bartlett
发明人： Daniel G. Knierim , James S. Lamb , Josiah A. Bartlett
IPC分类号： H04L25/00
CPC分类号： H01P5/10 , H01P1/184
摘要： A balun structure is disclosed having positive and negative going signal paths coupled to a ninety degree hybrid. The positive signal path has a circuit trace and a phase shaper structure that provides three hundred and sixty degrees of phase shift at Port 1 of the hybrid. The negative going signal path has a circuit trace and a second order phase shaper that provides four hundred and fifty degrees of phase shift at Port 2 of the hybrid. Port 1 is coupled to Port 3 of the hybrid and functions as an output port. The first order phase shaper and the second order phase shaper compensate for the signal loss caused by a signal cable coupled to the output port and provide a frequency band from DC to at least 15 GHz and a transient response having less than ten percent pre-shoot.
摘要翻译：公开了一种平衡 - 不平衡变换器结构，其具有耦合到九十度混合的正向和负向信号路径。正信号路径具有电路迹线和相位整形器结构，其在混合端口1处提供三百六十度的相移。负向信号路径具有电路迹线和二阶相位成形器，其在混合物的端口2处提供四百五十度的相移。端口1耦合到混合端口3，并用作输出端口。第一阶相位整形器和二阶相位整形器补偿由耦合到输出端口的信号电缆引起的信号损耗，并提供从DC到至少15GHz的频带和具有小于10％的预拍摄的瞬态响应。

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