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1. 发明授权

US08427896B1 Dynamic wordline assist scheme to improve performance tradeoff in SRAM 有权
标题翻译：动态字线辅助方案，以提高SRAM中的性能折衷
公开(公告)号：US08427896B1
公开(公告)日：2013-04-23
申请号：US13296724
申请日：2011-11-15
申请人： Pankaj Agarwal , Vaibhav V. Prabhu , Krishnan S. Rengarajan
发明人： Pankaj Agarwal , Vaibhav V. Prabhu , Krishnan S. Rengarajan
IPC分类号： G11C7/02
CPC分类号： G11C11/418 , G11C8/08
摘要： A dynamic wordline assist circuit for improving performance of an SRAM. An SRAM is disclosed that includes a plurality of memory cells, wherein each memory cell is coupled to a wordline and a pair of bitlines; and a wordline assist circuit coupled to the wordline, wherein the wordline assist circuit includes a first input for activating the wordline assist circuit during a read or write cycle and includes a second input for deactivating the wordline assist circuit during the read or write cycle after a delay.
摘要翻译：一种用于提高SRAM性能的动态字线辅助电路。公开了一种SRAM，其包括多个存储器单元，其中每个存储器单元耦合到字线和一对位线; 以及字线辅助电路，其耦合到所述字线，其中所述字线辅助电路包括用于在读取或写入周期期间激活所述字线辅助电路的第一输入，并且包括第二输入，用于在读取或写入周期之后停用所述字线辅助电路延迟。

2. 发明申请

US20130121065A1 DYNAMIC WORDLINE ASSIST SCHEME TO IMPROVE PERFORMANCE TRADEOFF IN SRAM 有权
标题翻译：动态WORDLINE协助计划提高SRAM中的性能交易
公开(公告)号：US20130121065A1
公开(公告)日：2013-05-16
申请号：US13296724
申请日：2011-11-15
申请人： Pankaj Agarwal , Vaibhav V. Prabhu , Krishnan S. Rengarajan
发明人： Pankaj Agarwal , Vaibhav V. Prabhu , Krishnan S. Rengarajan
IPC分类号： G11C11/00
CPC分类号： G11C11/418 , G11C8/08
摘要： A dynamic wordline assist circuit for improving performance of an SRAM. An SRAM is disclosed that includes a plurality of memory cells, wherein each memory cell is coupled to a wordline and a pair of bitlines; and a wordline assist circuit coupled to the wordline, wherein the wordline assist circuit includes a first input for activating the wordline assist circuit during a read or write cycle and includes a second input for deactivating the wordline assist circuit during the read or write cycle after a delay.
摘要翻译：一种用于提高SRAM性能的动态字线辅助电路。公开了一种SRAM，其包括多个存储器单元，其中每个存储器单元耦合到字线和一对位线; 以及字线辅助电路，其耦合到所述字线，其中所述字线辅助电路包括用于在读取或写入周期期间激活所述字线辅助电路的第一输入，并且包括第二输入，用于在读取或写入周期之后停用所述字线辅助电路延迟。

3. 发明授权

US09047980B2 Sense amplifier for static random access memory with a pair of complementary data lines isolated from a corresponding pair of complementary bit lines 有权
标题翻译：用于静态随机存取存储器的检测放大器，具有从相应的互补位线对分离的一对互补数据线
公开(公告)号：US09047980B2
公开(公告)日：2015-06-02
申请号：US13563960
申请日：2012-08-01
申请人： Pankaj Agarwal , Shiju K. Kandiyil , Krishnan S. Rengarajan
发明人： Pankaj Agarwal , Shiju K. Kandiyil , Krishnan S. Rengarajan
IPC分类号： G11C7/06 , G11C11/419 , G11C7/12
CPC分类号： G11C11/419 , G11C7/065 , G11C7/12
摘要： A sense amplifier for a static random access memory (SRAM) is described. In one embodiment, a first pass gate transistor is driven by a bit line true associated with an SRAM cell. A second pass gate transistor is driven by a bit line complement associated with the SRAM cell. A first pull down transistor is coupled to the first pass gate transistor and a second pull down transistor is coupled to the second pass gate transistor. A data line true is coupled to a node coupling the first pull down transistor with the first pass gate transistor. A data line complement is coupled to a node coupling the second pull down transistor with the second pass gate transistor.
摘要翻译：描述了用于静态随机存取存储器（SRAM）的读出放大器。在一个实施例中，第一传输栅极晶体管由与SRAM单元相关联的位线真实驱动。第二通栅晶体管由与SRAM单元相关联的位线补码驱动。第一下拉晶体管耦合到第一栅极晶体管，第二下拉晶体管耦合到第二栅极晶体管。数据线true耦合到将第一下拉晶体管与第一通路栅极晶体管耦合的节点。数据线补码耦合到将第二下拉晶体管与第二通过栅极晶体管耦合的节点。

4. 发明申请

US20140036581A1 SENSE AMPLIFIER FOR STATIC RANDOM ACCESS MEMORY 有权
标题翻译：用于静态随机存取存储器的SENSE放大器
公开(公告)号：US20140036581A1
公开(公告)日：2014-02-06
申请号：US13563960
申请日：2012-08-01
申请人： Pankaj Agarwal , Shiju K. Kandiyil , Krishnan S. Rengarajan
发明人： Pankaj Agarwal , Shiju K. Kandiyil , Krishnan S. Rengarajan
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/065 , G11C7/12
摘要： A sense amplifier for a static random access memory (SRAM) is described. In one embodiment, a first pass gate transistor is driven by a bit line true associated with an SRAM cell. A second pass gate transistor is driven by a bit line complement associated with the SRAM cell. A first pull down transistor is coupled to the first pass gate transistor and a second pull down transistor is coupled to the second pass gate transistor. A data line true is coupled to a node coupling the first pull down transistor with the first pass gate transistor. A data line complement is coupled to a node coupling the second pull down transistor with the second pass gate transistor.
摘要翻译：描述了用于静态随机存取存储器（SRAM）的读出放大器。在一个实施例中，第一传输栅极晶体管由与SRAM单元相关联的位线真实驱动。第二通栅晶体管由与SRAM单元相关联的位线补码驱动。第一下拉晶体管耦合到第一栅极晶体管，第二下拉晶体管耦合到第二栅极晶体管。数据线true耦合到将第一下拉晶体管与第一通路栅极晶体管耦合的节点。数据线补码耦合到将第二下拉晶体管与第二通过栅极晶体管耦合的节点。

5. 发明申请

US20090147605A1 NOVEL HIGH PERFORMANCE, AREA EFFICIENT DIRECT BITLINE SENSING CIRCUIT 有权
标题翻译：高性能，高效的直接感应电路
公开(公告)号：US20090147605A1
公开(公告)日：2009-06-11
申请号：US11953075
申请日：2007-12-10
申请人： Krishnan S. Rengarajan , Suresh Balasubramanian
发明人： Krishnan S. Rengarajan , Suresh Balasubramanian
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/02
摘要： In a method and apparatus for reading a logic state stored in an 8 transistor memory cell (8TMC), a differential sense circuit includes a differential input circuit having a pair of differential inputs and an output. An output signal is provided at the output and is indicative of a difference between two signals received at the pair of differential inputs. The difference is in accordance with the logic state read from the 8TMC. A sense amplifier is coupled to the output, the sense amplifier being operable to amplify the output signal that is greater than a threshold and switch the output signal to a voltage level corresponding to the logic state. The difference between the two signals measurable over a configurable time period is greater than a corresponding change in any one of the two signals measured over the same period, thereby improving the performance of the 8TMC.
摘要翻译：在用于读取存储在8晶体管存储单元（8TMC）中的逻辑状态的方法和装置中，差分检测电路包括具有一对差分输入和输出的差分输入电路。在输出处提供输出信号，并且指示在该对差分输入处接收的两个信号之间的差异。区别在于从8TMC读取的逻辑状态。感测放大器耦合到输出，读出放大器可操作以放大大于阈值的输出信号，并将输出信号切换到对应于逻辑状态的电压电平。在可配置的时间段内可测量的两个信号之间的差异大于在相同周期内测量的两个信号中的任何一个信号中相应的变化，从而提高8TMC的性能。

6. 发明授权

US08797096B2 Crosstalk compensation for high speed, reduced swing circuits 有权
标题翻译：串扰补偿为高速，减少摆幅电路
公开(公告)号：US08797096B2
公开(公告)日：2014-08-05
申请号：US13316067
申请日：2011-12-09
申请人： Prasad S. Nalawade , Veena Prabhu , Krishnan S. Rengarajan
发明人： Prasad S. Nalawade , Veena Prabhu , Krishnan S. Rengarajan
IPC分类号： H03K5/00
CPC分类号： G06F17/5063 , G06F2217/82
摘要： Structures and methods are provided for reducing or eliminating crosstalk in devices. Based on a predetermined compensation schemes, a compensation scheme is selected that minimizes the deviation of the non-aggressed victim signal caused by one or more aggressor signals. Instances of a compensation circuit corresponding to the selected compensation scheme are placed along a victim signal line at locations defined by the compensation scheme.
摘要翻译：提供了用于减少或消除器件串扰的结构和方法。基于预定的补偿方案，选择最小化由一个或多个攻击者信号引起的非受侵害的受害者信号的偏差的补偿方案。对应于所选择的补偿方案的补偿电路的实例沿着由补偿方案限定的位置处的受害信号线放置。

7. 发明授权

US08593861B2 Asymmetric memory cells 有权
标题翻译：不对称记忆细胞
公开(公告)号：US08593861B2
公开(公告)日：2013-11-26
申请号：US13269942
申请日：2011-10-10
申请人： George M. Braceras , Krishnan S. Rengarajan
发明人： George M. Braceras , Krishnan S. Rengarajan
IPC分类号： G11C11/00
CPC分类号： G11C7/20 , G11C11/412
摘要： An asymmetric memory cell is disclosed. The memory cell includes a refresh control line, a pass gate transistor, and a refresh transistor. The refresh transistor is coupled to the refresh control line, and provides a feedback between the pass gate transistor and a plurality of inverters, when the refresh control line is in a default state.
摘要翻译：公开了一种非对称存储器单元。存储单元包括刷新控制线，通栅晶体管和刷新晶体管。当刷新控制线处于默认状态时，刷新晶体管耦合到刷新控制线，并且在通过栅极晶体管和多个反相器之间提供反馈。

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